1 // SPDX-License-Identifier: GPL-2.0
82 	"vdda-pll", "vdda33", "vdda18",
110  * struct qcom_snps_hsphy - snps hs phy attributes
143 	struct device *dev = hsphy->dev;  in qcom_snps_hsphy_clk_init()
145 	hsphy->num_clks = 2;  in qcom_snps_hsphy_clk_init()
146 	hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL);  in qcom_snps_hsphy_clk_init()
147 	if (!hsphy->clks)  in qcom_snps_hsphy_clk_init()
148 		return -ENOMEM;  in qcom_snps_hsphy_clk_init()
154 	hsphy->clks[0].id = "cfg_ahb";  in qcom_snps_hsphy_clk_init()
155 	hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb");  in qcom_snps_hsphy_clk_init()
156 	if (IS_ERR(hsphy->clks[0].clk))  in qcom_snps_hsphy_clk_init()
157 		return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk),  in qcom_snps_hsphy_clk_init()
160 	hsphy->clks[1].id = "ref";  in qcom_snps_hsphy_clk_init()
161 	hsphy->clks[1].clk = devm_clk_get(dev, "ref");  in qcom_snps_hsphy_clk_init()
162 	if (IS_ERR(hsphy->clks[1].clk))  in qcom_snps_hsphy_clk_init()
163 		return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk),  in qcom_snps_hsphy_clk_init()
185 	dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");  in qcom_snps_hsphy_suspend()
187 	if (hsphy->mode == PHY_MODE_USB_HOST) {  in qcom_snps_hsphy_suspend()
188 		/* Enable auto-resume to meet remote wakeup timing */  in qcom_snps_hsphy_suspend()
189 		qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_suspend()
194 		qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_suspend()
204 	dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");  in qcom_snps_hsphy_resume()
213 	if (!hsphy->phy_initialized)  in qcom_snps_hsphy_runtime_suspend()
223 	if (!hsphy->phy_initialized)  in qcom_snps_hsphy_runtime_resume()
234 	hsphy->mode = mode;  in qcom_snps_hsphy_set_mode()
239 	{ -272, 0 },
250 	{ -2090, 7 },
251 	{ -1560, 6 },
252 	{ -1030, 5 },
253 	{ -530, 4 },
261 	{ -660, 0 },
262 	{ -440, 1 },
263 	{ -220, 2 },
292 	{ -4100, 3 },
299 	{ -31000, 1 },
305 	{ -2300000, 3 },
312 	{ -1053, 15 },
313 	{ -557, 7 },
321 		"qcom,hs-disconnect-bp",
328 		"qcom,squelch-detector-bp",
335 		"qcom,hs-amplitude-bp",
342 		"qcom,pre-emphasis-duration-bp",
349 		"qcom,pre-emphasis-amplitude-bp",
356 		"qcom,hs-rise-fall-time-bp",
363 		"qcom,hs-crossover-voltage-microvolt",
370 		"qcom,hs-output-impedance-micro-ohms",
377 		"qcom,ls-fs-output-impedance-bp",
391 	dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);  in qcom_snps_hsphy_init()
393 	ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_init()
397 	ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks);  in qcom_snps_hsphy_init()
399 		dev_err(&phy->dev, "failed to enable clocks, %d\n", ret);  in qcom_snps_hsphy_init()
403 	ret = reset_control_assert(hsphy->phy_reset);  in qcom_snps_hsphy_init()
405 		dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);  in qcom_snps_hsphy_init()
411 	ret = reset_control_deassert(hsphy->phy_reset);  in qcom_snps_hsphy_init()
413 		dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);  in qcom_snps_hsphy_init()
417 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,  in qcom_snps_hsphy_init()
420 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,  in qcom_snps_hsphy_init()
422 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
425 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
428 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,  in qcom_snps_hsphy_init()
430 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
433 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,  in qcom_snps_hsphy_init()
436 	for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {  in qcom_snps_hsphy_init()
437 		if (hsphy->update_seq_cfg[i].need_update)  in qcom_snps_hsphy_init()
438 			qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
439 					hsphy->update_seq_cfg[i].offset,  in qcom_snps_hsphy_init()
440 					hsphy->update_seq_cfg[i].mask,  in qcom_snps_hsphy_init()
441 					hsphy->update_seq_cfg[i].value);  in qcom_snps_hsphy_init()
444 	qcom_snps_hsphy_write_mask(hsphy->base,  in qcom_snps_hsphy_init()
448 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,  in qcom_snps_hsphy_init()
452 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,  in qcom_snps_hsphy_init()
455 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,  in qcom_snps_hsphy_init()
458 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,  in qcom_snps_hsphy_init()
461 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,  in qcom_snps_hsphy_init()
464 	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,  in qcom_snps_hsphy_init()
467 	hsphy->phy_initialized = true;  in qcom_snps_hsphy_init()
472 	clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);  in qcom_snps_hsphy_init()
474 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_init()
483 	reset_control_assert(hsphy->phy_reset);  in qcom_snps_hsphy_exit()
484 	clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks);  in qcom_snps_hsphy_exit()
485 	regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);  in qcom_snps_hsphy_exit()
486 	hsphy->phy_initialized = false;  in qcom_snps_hsphy_exit()
499 	{ .compatible	= "qcom,sm8150-usb-hs-phy", },
500 	{ .compatible	= "qcom,usb-snps-hs-5nm-phy", },
502 		.compatible	= "qcom,usb-snps-hs-7nm-phy",
505 	{ .compatible	= "qcom,usb-snps-femto-v2-phy",	},
527 	for (i = 0; i < map.table_size - 1; i++) {  in qcom_snps_hsphy_override_param_update_val()
532 	seq_entry->need_update = true;  in qcom_snps_hsphy_override_param_update_val()
533 	seq_entry->offset = map.reg_offset;  in qcom_snps_hsphy_override_param_update_val()
534 	seq_entry->mask = map.param_mask;  in qcom_snps_hsphy_override_param_update_val()
535 	seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask);  in qcom_snps_hsphy_override_param_update_val()
540 	struct device_node *node = dev->of_node;  in qcom_snps_hsphy_read_override_param_seq()
557 					&hsphy->update_seq_cfg[i]);  in qcom_snps_hsphy_read_override_param_seq()
558 		dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n",  in qcom_snps_hsphy_read_override_param_seq()
559 			cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value);  in qcom_snps_hsphy_read_override_param_seq()
566 	struct device *dev = &pdev->dev;  in qcom_snps_hsphy_probe()
575 		return -ENOMEM;  in qcom_snps_hsphy_probe()
577 	hsphy->dev = dev;  in qcom_snps_hsphy_probe()
579 	hsphy->base = devm_platform_ioremap_resource(pdev, 0);  in qcom_snps_hsphy_probe()
580 	if (IS_ERR(hsphy->base))  in qcom_snps_hsphy_probe()
581 		return PTR_ERR(hsphy->base);  in qcom_snps_hsphy_probe()
587 	hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in qcom_snps_hsphy_probe()
588 	if (IS_ERR(hsphy->phy_reset)) {  in qcom_snps_hsphy_probe()
590 		return PTR_ERR(hsphy->phy_reset);  in qcom_snps_hsphy_probe()
593 	num = ARRAY_SIZE(hsphy->vregs);  in qcom_snps_hsphy_probe()
595 		hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];  in qcom_snps_hsphy_probe()
597 	ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);  in qcom_snps_hsphy_probe()
616 	hsphy->phy = generic_phy;  in qcom_snps_hsphy_probe()
624 		dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");  in qcom_snps_hsphy_probe()
634 		.name	= "qcom-snps-hs-femto-v2-phy",