Lines Matching refs:regmap
29 struct regmap *regmap; member
34 static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) in qcom_dwmac_sgmii_phy_init_1g() argument
36 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
37 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
39 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
40 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); in qcom_dwmac_sgmii_phy_init_1g()
41 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16); in qcom_dwmac_sgmii_phy_init_1g()
42 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_1g()
43 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
44 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
45 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A); in qcom_dwmac_sgmii_phy_init_1g()
46 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x82); in qcom_dwmac_sgmii_phy_init_1g()
47 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55); in qcom_dwmac_sgmii_phy_init_1g()
48 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55); in qcom_dwmac_sgmii_phy_init_1g()
49 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03); in qcom_dwmac_sgmii_phy_init_1g()
50 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24); in qcom_dwmac_sgmii_phy_init_1g()
52 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02); in qcom_dwmac_sgmii_phy_init_1g()
53 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
54 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x04); in qcom_dwmac_sgmii_phy_init_1g()
55 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
56 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
57 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
58 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9); in qcom_dwmac_sgmii_phy_init_1g()
59 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E); in qcom_dwmac_sgmii_phy_init_1g()
60 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); in qcom_dwmac_sgmii_phy_init_1g()
62 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x05); in qcom_dwmac_sgmii_phy_init_1g()
63 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
64 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
65 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
66 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05); in qcom_dwmac_sgmii_phy_init_1g()
67 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
68 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12); in qcom_dwmac_sgmii_phy_init_1g()
69 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
71 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
72 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06); in qcom_dwmac_sgmii_phy_init_1g()
73 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
74 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); in qcom_dwmac_sgmii_phy_init_1g()
75 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
76 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
77 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81); in qcom_dwmac_sgmii_phy_init_1g()
78 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80); in qcom_dwmac_sgmii_phy_init_1g()
79 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x04); in qcom_dwmac_sgmii_phy_init_1g()
80 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_1g()
81 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
82 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); in qcom_dwmac_sgmii_phy_init_1g()
83 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
84 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); in qcom_dwmac_sgmii_phy_init_1g()
85 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); in qcom_dwmac_sgmii_phy_init_1g()
86 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80); in qcom_dwmac_sgmii_phy_init_1g()
87 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
88 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20); in qcom_dwmac_sgmii_phy_init_1g()
89 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); in qcom_dwmac_sgmii_phy_init_1g()
90 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
91 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F); in qcom_dwmac_sgmii_phy_init_1g()
92 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); in qcom_dwmac_sgmii_phy_init_1g()
93 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x05); in qcom_dwmac_sgmii_phy_init_1g()
94 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_1g()
95 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
96 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
97 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
98 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB1); in qcom_dwmac_sgmii_phy_init_1g()
99 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_1g()
100 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
101 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
102 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09); in qcom_dwmac_sgmii_phy_init_1g()
103 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1); in qcom_dwmac_sgmii_phy_init_1g()
104 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_1g()
105 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
106 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_1g()
107 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B); in qcom_dwmac_sgmii_phy_init_1g()
108 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); in qcom_dwmac_sgmii_phy_init_1g()
109 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
111 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
112 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); in qcom_dwmac_sgmii_phy_init_1g()
113 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); in qcom_dwmac_sgmii_phy_init_1g()
114 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); in qcom_dwmac_sgmii_phy_init_1g()
115 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_1g()
116 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C); in qcom_dwmac_sgmii_phy_init_1g()
117 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); in qcom_dwmac_sgmii_phy_init_1g()
119 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); in qcom_dwmac_sgmii_phy_init_1g()
122 static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) in qcom_dwmac_sgmii_phy_init_2p5g() argument
124 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
125 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
127 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); in qcom_dwmac_sgmii_phy_init_2p5g()
128 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); in qcom_dwmac_sgmii_phy_init_2p5g()
129 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16); in qcom_dwmac_sgmii_phy_init_2p5g()
130 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36); in qcom_dwmac_sgmii_phy_init_2p5g()
131 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A); in qcom_dwmac_sgmii_phy_init_2p5g()
132 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x1A); in qcom_dwmac_sgmii_phy_init_2p5g()
133 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x41); in qcom_dwmac_sgmii_phy_init_2p5g()
134 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x7A); in qcom_dwmac_sgmii_phy_init_2p5g()
135 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
136 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x20); in qcom_dwmac_sgmii_phy_init_2p5g()
137 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
138 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xA1); in qcom_dwmac_sgmii_phy_init_2p5g()
140 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02); in qcom_dwmac_sgmii_phy_init_2p5g()
141 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
142 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x03); in qcom_dwmac_sgmii_phy_init_2p5g()
143 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
144 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x05); in qcom_dwmac_sgmii_phy_init_2p5g()
145 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
146 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD); in qcom_dwmac_sgmii_phy_init_2p5g()
147 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C); in qcom_dwmac_sgmii_phy_init_2p5g()
148 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); in qcom_dwmac_sgmii_phy_init_2p5g()
150 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x04); in qcom_dwmac_sgmii_phy_init_2p5g()
151 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
152 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09); in qcom_dwmac_sgmii_phy_init_2p5g()
153 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x02); in qcom_dwmac_sgmii_phy_init_2p5g()
154 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05); in qcom_dwmac_sgmii_phy_init_2p5g()
155 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
156 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12); in qcom_dwmac_sgmii_phy_init_2p5g()
157 regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
159 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
160 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06); in qcom_dwmac_sgmii_phy_init_2p5g()
161 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
162 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); in qcom_dwmac_sgmii_phy_init_2p5g()
163 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
164 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
165 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81); in qcom_dwmac_sgmii_phy_init_2p5g()
166 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80); in qcom_dwmac_sgmii_phy_init_2p5g()
167 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
168 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_2p5g()
169 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F); in qcom_dwmac_sgmii_phy_init_2p5g()
170 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); in qcom_dwmac_sgmii_phy_init_2p5g()
171 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
172 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); in qcom_dwmac_sgmii_phy_init_2p5g()
173 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); in qcom_dwmac_sgmii_phy_init_2p5g()
174 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80); in qcom_dwmac_sgmii_phy_init_2p5g()
175 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
176 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20); in qcom_dwmac_sgmii_phy_init_2p5g()
177 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); in qcom_dwmac_sgmii_phy_init_2p5g()
178 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
179 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F); in qcom_dwmac_sgmii_phy_init_2p5g()
180 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); in qcom_dwmac_sgmii_phy_init_2p5g()
181 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x18); in qcom_dwmac_sgmii_phy_init_2p5g()
182 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0x18); in qcom_dwmac_sgmii_phy_init_2p5g()
183 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
184 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
185 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
186 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB8); in qcom_dwmac_sgmii_phy_init_2p5g()
187 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_2p5g()
188 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
189 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
190 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09); in qcom_dwmac_sgmii_phy_init_2p5g()
191 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1); in qcom_dwmac_sgmii_phy_init_2p5g()
192 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0); in qcom_dwmac_sgmii_phy_init_2p5g()
193 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
194 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8); in qcom_dwmac_sgmii_phy_init_2p5g()
195 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B); in qcom_dwmac_sgmii_phy_init_2p5g()
196 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); in qcom_dwmac_sgmii_phy_init_2p5g()
197 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
199 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); in qcom_dwmac_sgmii_phy_init_2p5g()
200 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); in qcom_dwmac_sgmii_phy_init_2p5g()
201 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); in qcom_dwmac_sgmii_phy_init_2p5g()
202 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); in qcom_dwmac_sgmii_phy_init_2p5g()
203 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); in qcom_dwmac_sgmii_phy_init_2p5g()
204 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C); in qcom_dwmac_sgmii_phy_init_2p5g()
205 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); in qcom_dwmac_sgmii_phy_init_2p5g()
207 regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); in qcom_dwmac_sgmii_phy_init_2p5g()
211 qcom_dwmac_sgmii_phy_poll_status(struct regmap *regmap, unsigned int reg, in qcom_dwmac_sgmii_phy_poll_status() argument
216 return regmap_read_poll_timeout(regmap, reg, val, in qcom_dwmac_sgmii_phy_poll_status()
229 qcom_dwmac_sgmii_phy_init_1g(data->regmap); in qcom_dwmac_sgmii_phy_calibrate()
232 qcom_dwmac_sgmii_phy_init_2p5g(data->regmap); in qcom_dwmac_sgmii_phy_calibrate()
236 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, in qcom_dwmac_sgmii_phy_calibrate()
243 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, in qcom_dwmac_sgmii_phy_calibrate()
250 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, in qcom_dwmac_sgmii_phy_calibrate()
257 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, in qcom_dwmac_sgmii_phy_calibrate()
278 regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); in qcom_dwmac_sgmii_phy_power_off()
279 regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); in qcom_dwmac_sgmii_phy_power_off()
281 regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); in qcom_dwmac_sgmii_phy_power_off()
282 regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); in qcom_dwmac_sgmii_phy_power_off()
333 data->regmap = devm_regmap_init_mmio(dev, base, in qcom_dwmac_sgmii_phy_probe()
335 if (IS_ERR(data->regmap)) in qcom_dwmac_sgmii_phy_probe()
336 return PTR_ERR(data->regmap); in qcom_dwmac_sgmii_phy_probe()