20 #define QSERDES_TX					0x400  macro
62 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x05);  in qcom_dwmac_sgmii_phy_init_1g()
63 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A);  in qcom_dwmac_sgmii_phy_init_1g()
64 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09);  in qcom_dwmac_sgmii_phy_init_1g()
65 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09);  in qcom_dwmac_sgmii_phy_init_1g()
66 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05);  in qcom_dwmac_sgmii_phy_init_1g()
67 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00);  in qcom_dwmac_sgmii_phy_init_1g()
68 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12);  in qcom_dwmac_sgmii_phy_init_1g()
69 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C);  in qcom_dwmac_sgmii_phy_init_1g()
150 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x04);  in qcom_dwmac_sgmii_phy_init_2p5g()
151 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A);  in qcom_dwmac_sgmii_phy_init_2p5g()
152 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09);  in qcom_dwmac_sgmii_phy_init_2p5g()
153 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x02);  in qcom_dwmac_sgmii_phy_init_2p5g()
154 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05);  in qcom_dwmac_sgmii_phy_init_2p5g()
155 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00);  in qcom_dwmac_sgmii_phy_init_2p5g()
156 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12);  in qcom_dwmac_sgmii_phy_init_2p5g()
157 	regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C);  in qcom_dwmac_sgmii_phy_init_2p5g()