Lines Matching +full:syscon +full:- +full:efuse
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/mfd/syscon.h>
13 #include <linux/nvmem-consumer.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
322 /* true if PHY default clk scheme is single-ended */
422 "vdd", "vdda-pll", "vdda-phy-dpdm",
427 /* struct override_param - structure holding qusb2 v2 phy overriding param
436 /*struct override_params - structure holding qusb2 v2 phy overriding params
439 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
440 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
456 * struct qusb2_phy - structure holding qusb2 phy attributes
467 * @tcsr: TCSR syscon register map
473 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
557 const struct qusb2_phy_cfg *cfg = qphy->cfg;
558 struct override_params *or = &qphy->overrides;
560 if (or->imp_res_offset.override)
561 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
562 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
565 if (or->bias_ctrl.override)
566 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
567 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
570 if (or->charge_ctrl.override)
571 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
572 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
575 if (or->hstx_trim.override)
576 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
577 or->hstx_trim.value << HSTX_TRIM_SHIFT,
580 if (or->preemphasis.override)
581 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
582 or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
585 if (or->preemphasis_width.override) {
586 if (or->preemphasis_width.value ==
588 qusb2_setbits(qphy->base,
589 cfg->regs[QUSB2PHY_PORT_TUNE1],
592 qusb2_clrbits(qphy->base,
593 cfg->regs[QUSB2PHY_PORT_TUNE1],
597 if (or->hsdisc_trim.override)
598 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
599 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
610 struct device *dev = &qphy->phy->dev;
611 const struct qusb2_phy_cfg *cfg = qphy->cfg;
614 /* efuse register is optional */
615 if (!qphy->cell)
619 * Read efuse register having TUNE2/1 parameter's high nibble.
620 * If efuse register shows value as 0x0 (indicating value is not
621 * fused), or if we fail to find a valid efuse register setting,
625 val = nvmem_cell_read(qphy->cell, NULL);
627 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
633 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
638 if (cfg->update_tune1_with_efuse)
639 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
642 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
651 qphy->mode = mode;
659 const struct qusb2_phy_cfg *cfg = qphy->cfg;
662 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
664 if (!qphy->phy_initialized) {
672 * current D+/D- levels are e.g. if currently D+ high, D- low
673 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
676 switch (qphy->mode) {
694 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
697 if (cfg->has_pll_override) {
698 qusb2_setbits(qphy->base,
699 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
704 /* enable phy auto-resume only if device is connected on bus */
705 if (qphy->mode != PHY_MODE_INVALID) {
706 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
707 cfg->autoresume_en);
709 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
710 cfg->autoresume_en);
713 if (!qphy->has_se_clk_scheme)
714 clk_disable_unprepare(qphy->ref_clk);
716 clk_disable_unprepare(qphy->cfg_ahb_clk);
717 clk_disable_unprepare(qphy->iface_clk);
725 const struct qusb2_phy_cfg *cfg = qphy->cfg;
728 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
730 if (!qphy->phy_initialized) {
735 ret = clk_prepare_enable(qphy->iface_clk);
741 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
747 if (!qphy->has_se_clk_scheme) {
748 ret = clk_prepare_enable(qphy->ref_clk);
755 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
758 if (cfg->has_pll_override) {
759 qusb2_clrbits(qphy->base,
760 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
767 clk_disable_unprepare(qphy->cfg_ahb_clk);
769 clk_disable_unprepare(qphy->iface_clk);
777 const struct qusb2_phy_cfg *cfg = qphy->cfg;
782 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
785 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
789 ret = clk_prepare_enable(qphy->iface_clk);
791 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
796 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
798 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
803 ret = reset_control_assert(qphy->phy_reset);
805 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
812 ret = reset_control_deassert(qphy->phy_reset);
814 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
819 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
820 qphy->cfg->disable_ctrl);
822 if (cfg->has_pll_test) {
824 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
827 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
828 cfg->tbl_num);
833 /* Set efuse value for tuning the PHY */
837 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
848 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
851 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
853 * ref_clk and use single-ended clock, otherwise use differential
856 if (qphy->tcsr) {
857 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
860 dev_err(&phy->dev, "failed to read clk scheme reg\n");
866 dev_vdbg(&phy->dev, "%s(): select differential clk\n",
868 qphy->has_se_clk_scheme = false;
870 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
875 if (!qphy->has_se_clk_scheme) {
876 ret = clk_prepare_enable(qphy->ref_clk);
878 dev_err(&phy->dev, "failed to enable ref clk, %d\n",
884 if (cfg->has_pll_test) {
885 if (!qphy->has_se_clk_scheme)
890 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
893 readl(qphy->base + QUSB2PHY_PLL_TEST);
899 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
900 if (!(val & cfg->mask_core_ready)) {
901 dev_err(&phy->dev,
903 ret = -EBUSY;
906 qphy->phy_initialized = true;
911 if (!qphy->has_se_clk_scheme)
912 clk_disable_unprepare(qphy->ref_clk);
914 reset_control_assert(qphy->phy_reset);
916 clk_disable_unprepare(qphy->cfg_ahb_clk);
918 clk_disable_unprepare(qphy->iface_clk);
920 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
930 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
931 qphy->cfg->disable_ctrl);
933 if (!qphy->has_se_clk_scheme)
934 clk_disable_unprepare(qphy->ref_clk);
936 reset_control_assert(qphy->phy_reset);
938 clk_disable_unprepare(qphy->cfg_ahb_clk);
939 clk_disable_unprepare(qphy->iface_clk);
941 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
943 qphy->phy_initialized = false;
957 .compatible = "qcom,ipq5424-qusb2-phy",
960 .compatible = "qcom,ipq6018-qusb2-phy",
963 .compatible = "qcom,ipq8074-qusb2-phy",
966 .compatible = "qcom,ipq9574-qusb2-phy",
969 .compatible = "qcom,msm8953-qusb2-phy",
972 .compatible = "qcom,msm8996-qusb2-phy",
975 .compatible = "qcom,msm8998-qusb2-phy",
978 .compatible = "qcom,qcs615-qusb2-phy",
981 .compatible = "qcom,qcm2290-qusb2-phy",
984 .compatible = "qcom,sdm660-qusb2-phy",
987 .compatible = "qcom,sm4250-qusb2-phy",
990 .compatible = "qcom,sm6115-qusb2-phy",
995 * trees that didn't include "qcom,qusb2-v2-phy"
997 .compatible = "qcom,sdm845-qusb2-phy",
1000 .compatible = "qcom,qusb2-v2-phy",
1014 struct device *dev = &pdev->dev;
1025 return -ENOMEM;
1026 or = &qphy->overrides;
1028 qphy->base = devm_platform_ioremap_resource(pdev, 0);
1029 if (IS_ERR(qphy->base))
1030 return PTR_ERR(qphy->base);
1032 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
1033 if (IS_ERR(qphy->cfg_ahb_clk))
1034 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk),
1037 qphy->ref_clk = devm_clk_get(dev, "ref");
1038 if (IS_ERR(qphy->ref_clk))
1039 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk),
1042 qphy->iface_clk = devm_clk_get_optional(dev, "iface");
1043 if (IS_ERR(qphy->iface_clk))
1044 return PTR_ERR(qphy->iface_clk);
1046 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
1047 if (IS_ERR(qphy->phy_reset)) {
1049 return PTR_ERR(qphy->phy_reset);
1052 num = ARRAY_SIZE(qphy->vregs);
1054 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
1056 ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
1062 qphy->cfg = of_device_get_match_data(dev);
1064 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
1065 "qcom,tcsr-syscon");
1066 if (IS_ERR(qphy->tcsr)) {
1068 qphy->tcsr = NULL;
1071 qphy->cell = devm_nvmem_cell_get(dev, NULL);
1072 if (IS_ERR(qphy->cell)) {
1073 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
1074 return -EPROBE_DEFER;
1075 qphy->cell = NULL;
1079 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
1081 or->imp_res_offset.value = (u8)value;
1082 or->imp_res_offset.override = true;
1085 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
1087 or->bias_ctrl.value = (u8)value;
1088 or->bias_ctrl.override = true;
1091 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
1093 or->charge_ctrl.value = (u8)value;
1094 or->charge_ctrl.override = true;
1097 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
1099 or->hstx_trim.value = (u8)value;
1100 or->hstx_trim.override = true;
1103 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
1105 or->preemphasis.value = (u8)value;
1106 or->preemphasis.override = true;
1109 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
1111 or->preemphasis_width.value = (u8)value;
1112 or->preemphasis_width.override = true;
1115 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
1117 or->hsdisc_trim.value = (u8)value;
1118 or->hsdisc_trim.override = true;
1136 qphy->phy = generic_phy;
1143 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
1153 .name = "qcom-qusb2-phy",