Lines Matching +full:default +full:- +full:trim
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
307 /* true if PHY default clk scheme is single-ended */
397 "vdd", "vdda-pll", "vdda-phy-dpdm",
402 /* struct override_param - structure holding qusb2 v2 phy overriding param
411 /*struct override_params - structure holding qusb2 v2 phy overriding params
414 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
415 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
431 * struct qusb2_phy - structure holding qusb2 phy attributes
448 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
532 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
533 struct override_params *or = &qphy->overrides; in qusb2_phy_override_phy_params()
535 if (or->imp_res_offset.override) in qusb2_phy_override_phy_params()
536 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
537 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
540 if (or->bias_ctrl.override) in qusb2_phy_override_phy_params()
541 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, in qusb2_phy_override_phy_params()
542 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
545 if (or->charge_ctrl.override) in qusb2_phy_override_phy_params()
546 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, in qusb2_phy_override_phy_params()
547 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
550 if (or->hstx_trim.override) in qusb2_phy_override_phy_params()
551 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
552 or->hstx_trim.value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
555 if (or->preemphasis.override) in qusb2_phy_override_phy_params()
556 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
557 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
560 if (or->preemphasis_width.override) { in qusb2_phy_override_phy_params()
561 if (or->preemphasis_width.value == in qusb2_phy_override_phy_params()
563 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
564 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
567 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
568 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
572 if (or->hsdisc_trim.override) in qusb2_phy_override_phy_params()
573 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_override_phy_params()
574 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, in qusb2_phy_override_phy_params()
581 * For error case, skip setting the value and use the default value.
585 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
586 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
590 if (!qphy->cell) in qusb2_phy_set_tune2_param()
597 * then use default value for high nibble that we have already in qusb2_phy_set_tune2_param()
600 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
602 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
608 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
613 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
614 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
617 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
626 qphy->mode = mode; in qusb2_phy_set_mode()
634 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
637 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
639 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
647 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
648 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
651 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
662 default: in qusb2_phy_runtime_suspend()
669 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
672 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
673 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
674 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
679 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
680 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
681 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
682 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
684 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
685 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
688 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
689 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
691 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
692 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
700 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
703 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
705 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
710 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
716 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
722 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
723 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
730 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
733 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
734 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
735 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
742 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
744 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
752 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
757 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
760 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
764 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
766 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
771 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
773 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
778 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
780 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
787 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
789 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
794 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
795 qphy->cfg->disable_ctrl); in qusb2_phy_init()
797 if (cfg->has_pll_test) { in qusb2_phy_init()
799 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
802 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
803 cfg->tbl_num); in qusb2_phy_init()
812 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
820 * register in the TCSR so, if there's none, use the default in qusb2_phy_init()
823 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; in qusb2_phy_init()
826 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
828 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
831 if (qphy->tcsr) { in qusb2_phy_init()
832 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
835 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
841 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
843 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
845 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
850 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
851 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
853 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
859 if (cfg->has_pll_test) { in qusb2_phy_init()
860 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
865 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
868 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
874 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
875 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
876 dev_err(&phy->dev, in qusb2_phy_init()
878 ret = -EBUSY; in qusb2_phy_init()
881 qphy->phy_initialized = true; in qusb2_phy_init()
886 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
887 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
889 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
891 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
893 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
895 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
905 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
906 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
908 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
909 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
911 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
913 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
914 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
916 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
918 qphy->phy_initialized = false; in qusb2_phy_exit()
932 .compatible = "qcom,ipq5424-qusb2-phy",
935 .compatible = "qcom,ipq6018-qusb2-phy",
938 .compatible = "qcom,ipq8074-qusb2-phy",
941 .compatible = "qcom,ipq9574-qusb2-phy",
944 .compatible = "qcom,msm8953-qusb2-phy",
947 .compatible = "qcom,msm8996-qusb2-phy",
950 .compatible = "qcom,msm8998-qusb2-phy",
953 .compatible = "qcom,qcs615-qusb2-phy",
956 .compatible = "qcom,qcm2290-qusb2-phy",
959 .compatible = "qcom,sdm660-qusb2-phy",
962 .compatible = "qcom,sm4250-qusb2-phy",
965 .compatible = "qcom,sm6115-qusb2-phy",
970 * trees that didn't include "qcom,qusb2-v2-phy"
972 .compatible = "qcom,sdm845-qusb2-phy",
975 .compatible = "qcom,qusb2-v2-phy",
989 struct device *dev = &pdev->dev; in qusb2_phy_probe()
1000 return -ENOMEM; in qusb2_phy_probe()
1001 or = &qphy->overrides; in qusb2_phy_probe()
1003 qphy->base = devm_platform_ioremap_resource(pdev, 0); in qusb2_phy_probe()
1004 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
1005 return PTR_ERR(qphy->base); in qusb2_phy_probe()
1007 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
1008 if (IS_ERR(qphy->cfg_ahb_clk)) in qusb2_phy_probe()
1009 return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk), in qusb2_phy_probe()
1012 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
1013 if (IS_ERR(qphy->ref_clk)) in qusb2_phy_probe()
1014 return dev_err_probe(dev, PTR_ERR(qphy->ref_clk), in qusb2_phy_probe()
1017 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); in qusb2_phy_probe()
1018 if (IS_ERR(qphy->iface_clk)) in qusb2_phy_probe()
1019 return PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
1021 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
1022 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
1024 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
1027 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
1029 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
1031 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
1037 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
1039 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
1040 "qcom,tcsr-syscon"); in qusb2_phy_probe()
1041 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
1043 qphy->tcsr = NULL; in qusb2_phy_probe()
1046 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
1047 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
1048 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
1049 return -EPROBE_DEFER; in qusb2_phy_probe()
1050 qphy->cell = NULL; in qusb2_phy_probe()
1051 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); in qusb2_phy_probe()
1054 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
1056 or->imp_res_offset.value = (u8)value; in qusb2_phy_probe()
1057 or->imp_res_offset.override = true; in qusb2_phy_probe()
1060 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", in qusb2_phy_probe()
1062 or->bias_ctrl.value = (u8)value; in qusb2_phy_probe()
1063 or->bias_ctrl.override = true; in qusb2_phy_probe()
1066 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", in qusb2_phy_probe()
1068 or->charge_ctrl.value = (u8)value; in qusb2_phy_probe()
1069 or->charge_ctrl.override = true; in qusb2_phy_probe()
1072 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
1074 or->hstx_trim.value = (u8)value; in qusb2_phy_probe()
1075 or->hstx_trim.override = true; in qusb2_phy_probe()
1078 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
1080 or->preemphasis.value = (u8)value; in qusb2_phy_probe()
1081 or->preemphasis.override = true; in qusb2_phy_probe()
1084 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
1086 or->preemphasis_width.value = (u8)value; in qusb2_phy_probe()
1087 or->preemphasis_width.override = true; in qusb2_phy_probe()
1090 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", in qusb2_phy_probe()
1092 or->hsdisc_trim.value = (u8)value; in qusb2_phy_probe()
1093 or->hsdisc_trim.override = true; in qusb2_phy_probe()
1099 * Prevent runtime pm from being ON by default. Users can enable in qusb2_phy_probe()
1111 qphy->phy = generic_phy; in qusb2_phy_probe()
1126 .name = "qcom-qusb2-phy",