Lines Matching +full:ufs +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include <ufs/unipro.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
34 #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
41 #define NUM_OVERLAY 2
43 /* set of registers with offsets different per-PHY */
1081 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1094 /* struct qmp_phy_cfg - per-PHY initialization config */
1102 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1169 "vdda-phy", "vdda-pll",
1214 .lanes = 2,
1248 .lanes = 2,
1282 .lanes = 2,
1316 .lanes = 2,
1397 .lanes = 2,
1431 .lanes = 2,
1465 .lanes = 2,
1499 .lanes = 2,
1533 .lanes = 2,
1569 .lanes = 2,
1614 .lanes = 2,
1646 .lanes = 2,
1686 void __iomem *serdes = qmp->serdes; in qmp_ufs_serdes_init()
1688 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_ufs_serdes_init()
1693 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_lanes_init()
1694 void __iomem *tx = qmp->tx; in qmp_ufs_lanes_init()
1695 void __iomem *rx = qmp->rx; in qmp_ufs_lanes_init()
1697 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); in qmp_ufs_lanes_init()
1698 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); in qmp_ufs_lanes_init()
1700 if (cfg->lanes >= 2) { in qmp_ufs_lanes_init()
1701 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2); in qmp_ufs_lanes_init()
1702 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2); in qmp_ufs_lanes_init()
1708 void __iomem *pcs = qmp->pcs; in qmp_ufs_pcs_init()
1710 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_ufs_pcs_init()
1715 u32 max_gear, floor_max_gear = cfg->max_supported_gear; in qmp_ufs_get_gear_overlay()
1716 int idx, ret = -EINVAL; in qmp_ufs_get_gear_overlay()
1718 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) { in qmp_ufs_get_gear_overlay()
1719 max_gear = cfg->tbls_hs_overlay[idx].max_gear; in qmp_ufs_get_gear_overlay()
1726 if (qmp->submode == max_gear) in qmp_ufs_get_gear_overlay()
1750 qmp_ufs_init_all(qmp, &cfg->tbls); in qmp_ufs_init_registers()
1754 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); in qmp_ufs_init_registers()
1757 if (qmp->mode == PHY_MODE_UFS_HS_B) in qmp_ufs_init_registers()
1758 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); in qmp_ufs_init_registers()
1763 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_com_init()
1764 void __iomem *pcs = qmp->pcs; in qmp_ufs_com_init()
1767 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_ufs_com_init()
1769 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_ufs_com_init()
1773 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); in qmp_ufs_com_init()
1777 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); in qmp_ufs_com_init()
1782 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_ufs_com_init()
1789 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_com_exit()
1791 reset_control_assert(qmp->ufs_reset); in qmp_ufs_com_exit()
1793 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_ufs_com_exit()
1795 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_ufs_com_exit()
1803 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_init()
1805 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); in qmp_ufs_init()
1807 if (cfg->no_pcs_sw_reset) { in qmp_ufs_init()
1809 * Get UFS reset, which is delayed until now to avoid a in qmp_ufs_init()
1810 * circular dependency where UFS needs its PHY, but the PHY in qmp_ufs_init()
1811 * needs this UFS reset. in qmp_ufs_init()
1813 if (!qmp->ufs_reset) { in qmp_ufs_init()
1814 qmp->ufs_reset = in qmp_ufs_init()
1815 devm_reset_control_get_exclusive(qmp->dev, in qmp_ufs_init()
1818 if (IS_ERR(qmp->ufs_reset)) { in qmp_ufs_init()
1819 ret = PTR_ERR(qmp->ufs_reset); in qmp_ufs_init()
1820 dev_err(qmp->dev, in qmp_ufs_init()
1821 "failed to get UFS reset: %d\n", in qmp_ufs_init()
1824 qmp->ufs_reset = NULL; in qmp_ufs_init()
1829 ret = reset_control_assert(qmp->ufs_reset); in qmp_ufs_init()
1844 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_power_on()
1845 void __iomem *pcs = qmp->pcs; in qmp_ufs_power_on()
1852 ret = reset_control_deassert(qmp->ufs_reset); in qmp_ufs_power_on()
1857 if (!cfg->no_pcs_sw_reset) in qmp_ufs_power_on()
1858 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_ufs_power_on()
1861 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); in qmp_ufs_power_on()
1863 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; in qmp_ufs_power_on()
1867 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_ufs_power_on()
1877 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_power_off()
1880 if (!cfg->no_pcs_sw_reset) in qmp_ufs_power_off()
1881 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_ufs_power_off()
1884 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); in qmp_ufs_power_off()
1887 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_ufs_power_off()
1930 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_set_mode()
1932 if (submode > cfg->max_supported_gear || submode == 0) { in qmp_ufs_set_mode()
1933 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode); in qmp_ufs_set_mode()
1934 return -EINVAL; in qmp_ufs_set_mode()
1937 qmp->mode = mode; in qmp_ufs_set_mode()
1938 qmp->submode = submode; in qmp_ufs_set_mode()
1952 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_vreg_init()
1953 struct device *dev = qmp->dev; in qmp_ufs_vreg_init()
1954 int num = cfg->num_vregs; in qmp_ufs_vreg_init()
1957 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_ufs_vreg_init()
1958 if (!qmp->vregs) in qmp_ufs_vreg_init()
1959 return -ENOMEM; in qmp_ufs_vreg_init()
1962 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_ufs_vreg_init()
1964 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_ufs_vreg_init()
1969 struct device *dev = qmp->dev; in qmp_ufs_clk_init()
1971 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks); in qmp_ufs_clk_init()
1972 if (qmp->num_clks < 0) in qmp_ufs_clk_init()
1973 return qmp->num_clks; in qmp_ufs_clk_init()
1992 clk_data = devm_kzalloc(qmp->dev, in qmp_ufs_register_clocks()
1996 return -ENOMEM; in qmp_ufs_register_clocks()
1998 clk_data->num = UFS_SYMBOL_CLOCKS; in qmp_ufs_register_clocks()
2000 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); in qmp_ufs_register_clocks()
2001 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); in qmp_ufs_register_clocks()
2005 clk_data->hws[0] = hw; in qmp_ufs_register_clocks()
2007 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); in qmp_ufs_register_clocks()
2008 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); in qmp_ufs_register_clocks()
2012 clk_data->hws[1] = hw; in qmp_ufs_register_clocks()
2014 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); in qmp_ufs_register_clocks()
2015 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); in qmp_ufs_register_clocks()
2019 clk_data->hws[2] = hw; in qmp_ufs_register_clocks()
2028 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); in qmp_ufs_register_clocks()
2033 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_ufs_parse_dt_legacy()
2034 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_parse_dt_legacy()
2035 struct device *dev = qmp->dev; in qmp_ufs_parse_dt_legacy()
2037 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_ufs_parse_dt_legacy()
2038 if (IS_ERR(qmp->serdes)) in qmp_ufs_parse_dt_legacy()
2039 return PTR_ERR(qmp->serdes); in qmp_ufs_parse_dt_legacy()
2043 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_ufs_parse_dt_legacy()
2044 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_ufs_parse_dt_legacy()
2045 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_ufs_parse_dt_legacy()
2047 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_ufs_parse_dt_legacy()
2048 if (IS_ERR(qmp->tx)) in qmp_ufs_parse_dt_legacy()
2049 return PTR_ERR(qmp->tx); in qmp_ufs_parse_dt_legacy()
2051 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_ufs_parse_dt_legacy()
2052 if (IS_ERR(qmp->rx)) in qmp_ufs_parse_dt_legacy()
2053 return PTR_ERR(qmp->rx); in qmp_ufs_parse_dt_legacy()
2055 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_ufs_parse_dt_legacy()
2056 if (IS_ERR(qmp->pcs)) in qmp_ufs_parse_dt_legacy()
2057 return PTR_ERR(qmp->pcs); in qmp_ufs_parse_dt_legacy()
2059 if (cfg->lanes >= 2) { in qmp_ufs_parse_dt_legacy()
2060 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_ufs_parse_dt_legacy()
2061 if (IS_ERR(qmp->tx2)) in qmp_ufs_parse_dt_legacy()
2062 return PTR_ERR(qmp->tx2); in qmp_ufs_parse_dt_legacy()
2064 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_ufs_parse_dt_legacy()
2065 if (IS_ERR(qmp->rx2)) in qmp_ufs_parse_dt_legacy()
2066 return PTR_ERR(qmp->rx2); in qmp_ufs_parse_dt_legacy()
2068 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_ufs_parse_dt_legacy()
2070 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_ufs_parse_dt_legacy()
2073 if (IS_ERR(qmp->pcs_misc)) in qmp_ufs_parse_dt_legacy()
2074 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); in qmp_ufs_parse_dt_legacy()
2081 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_ufs_parse_dt()
2082 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_ufs_parse_dt()
2083 const struct qmp_ufs_offsets *offs = cfg->offsets; in qmp_ufs_parse_dt()
2087 return -EINVAL; in qmp_ufs_parse_dt()
2093 qmp->serdes = base + offs->serdes; in qmp_ufs_parse_dt()
2094 qmp->pcs = base + offs->pcs; in qmp_ufs_parse_dt()
2095 qmp->tx = base + offs->tx; in qmp_ufs_parse_dt()
2096 qmp->rx = base + offs->rx; in qmp_ufs_parse_dt()
2098 if (cfg->lanes >= 2) { in qmp_ufs_parse_dt()
2099 qmp->tx2 = base + offs->tx2; in qmp_ufs_parse_dt()
2100 qmp->rx2 = base + offs->rx2; in qmp_ufs_parse_dt()
2108 struct device *dev = &pdev->dev; in qmp_ufs_probe()
2116 return -ENOMEM; in qmp_ufs_probe()
2118 qmp->dev = dev; in qmp_ufs_probe()
2120 qmp->cfg = of_device_get_match_data(dev); in qmp_ufs_probe()
2121 if (!qmp->cfg) in qmp_ufs_probe()
2122 return -EINVAL; in qmp_ufs_probe()
2133 np = of_get_next_available_child(dev->of_node, NULL); in qmp_ufs_probe()
2137 np = of_node_get(dev->of_node); in qmp_ufs_probe()
2147 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); in qmp_ufs_probe()
2148 if (IS_ERR(qmp->phy)) { in qmp_ufs_probe()
2149 ret = PTR_ERR(qmp->phy); in qmp_ufs_probe()
2154 phy_set_drvdata(qmp->phy, qmp); in qmp_ufs_probe()
2169 .compatible = "qcom,msm8996-qmp-ufs-phy",
2172 .compatible = "qcom,msm8998-qmp-ufs-phy",
2175 .compatible = "qcom,sa8775p-qmp-ufs-phy",
2178 .compatible = "qcom,sc7180-qmp-ufs-phy",
2181 .compatible = "qcom,sc7280-qmp-ufs-phy",
2184 .compatible = "qcom,sc8180x-qmp-ufs-phy",
2187 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
2190 .compatible = "qcom,sdm845-qmp-ufs-phy",
2193 .compatible = "qcom,sm6115-qmp-ufs-phy",
2196 .compatible = "qcom,sm6125-qmp-ufs-phy",
2199 .compatible = "qcom,sm6350-qmp-ufs-phy",
2202 .compatible = "qcom,sm7150-qmp-ufs-phy",
2205 .compatible = "qcom,sm8150-qmp-ufs-phy",
2208 .compatible = "qcom,sm8250-qmp-ufs-phy",
2211 .compatible = "qcom,sm8350-qmp-ufs-phy",
2214 .compatible = "qcom,sm8450-qmp-ufs-phy",
2217 .compatible = "qcom,sm8475-qmp-ufs-phy",
2220 .compatible = "qcom,sm8550-qmp-ufs-phy",
2223 .compatible = "qcom,sm8650-qmp-ufs-phy",
2226 .compatible = "qcom,sm8750-qmp-ufs-phy",
2237 .name = "qcom-qmp-ufs-phy",
2245 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");