Lines Matching +full:regulator +full:- +full:v6
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
18 #include <linux/regulator/consumer.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
34 #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
43 /* set of registers with offsets different per-PHY */
1081 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1094 /* struct qmp_phy_cfg - per-PHY initialization config */
1102 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1169 "vdda-phy", "vdda-pll",
1686 void __iomem *serdes = qmp->serdes;
1688 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
1693 const struct qmp_phy_cfg *cfg = qmp->cfg;
1694 void __iomem *tx = qmp->tx;
1695 void __iomem *rx = qmp->rx;
1697 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
1698 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
1700 if (cfg->lanes >= 2) {
1701 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2);
1702 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2);
1708 void __iomem *pcs = qmp->pcs;
1710 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
1715 u32 max_gear, floor_max_gear = cfg->max_supported_gear;
1716 int idx, ret = -EINVAL;
1718 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
1719 max_gear = cfg->tbls_hs_overlay[idx].max_gear;
1726 if (qmp->submode == max_gear)
1750 qmp_ufs_init_all(qmp, &cfg->tbls);
1754 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]);
1757 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
1762 const struct qmp_phy_cfg *cfg = qmp->cfg;
1763 void __iomem *pcs = qmp->pcs;
1766 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1768 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1772 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1776 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1781 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1788 const struct qmp_phy_cfg *cfg = qmp->cfg;
1790 reset_control_assert(qmp->ufs_reset);
1792 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1794 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1802 const struct qmp_phy_cfg *cfg = qmp->cfg;
1804 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1806 if (cfg->no_pcs_sw_reset) {
1812 if (!qmp->ufs_reset) {
1813 qmp->ufs_reset =
1814 devm_reset_control_get_exclusive(qmp->dev,
1817 if (IS_ERR(qmp->ufs_reset)) {
1818 ret = PTR_ERR(qmp->ufs_reset);
1819 dev_err(qmp->dev,
1823 qmp->ufs_reset = NULL;
1828 ret = reset_control_assert(qmp->ufs_reset);
1843 const struct qmp_phy_cfg *cfg = qmp->cfg;
1844 void __iomem *pcs = qmp->pcs;
1851 ret = reset_control_deassert(qmp->ufs_reset);
1856 if (!cfg->no_pcs_sw_reset)
1857 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1860 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1862 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1866 dev_err(qmp->dev, "phy initialization timed-out\n");
1876 const struct qmp_phy_cfg *cfg = qmp->cfg;
1879 if (!cfg->no_pcs_sw_reset)
1880 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1883 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1886 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1929 const struct qmp_phy_cfg *cfg = qmp->cfg;
1931 if (submode > cfg->max_supported_gear || submode == 0) {
1932 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
1933 return -EINVAL;
1936 qmp->mode = mode;
1937 qmp->submode = submode;
1951 const struct qmp_phy_cfg *cfg = qmp->cfg;
1952 struct device *dev = qmp->dev;
1953 int num = cfg->num_vregs;
1956 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1957 if (!qmp->vregs)
1958 return -ENOMEM;
1961 qmp->vregs[i].supply = cfg->vreg_list[i];
1963 return devm_regulator_bulk_get(dev, num, qmp->vregs);
1968 struct device *dev = qmp->dev;
1970 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks);
1971 if (qmp->num_clks < 0)
1972 return qmp->num_clks;
1991 clk_data = devm_kzalloc(qmp->dev,
1995 return -ENOMEM;
1997 clk_data->num = UFS_SYMBOL_CLOCKS;
1999 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
2000 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2004 clk_data->hws[0] = hw;
2006 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
2007 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2011 clk_data->hws[1] = hw;
2013 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
2014 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2018 clk_data->hws[2] = hw;
2027 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
2032 struct platform_device *pdev = to_platform_device(qmp->dev);
2033 const struct qmp_phy_cfg *cfg = qmp->cfg;
2034 struct device *dev = qmp->dev;
2036 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2037 if (IS_ERR(qmp->serdes))
2038 return PTR_ERR(qmp->serdes);
2042 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2043 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2044 * For single lane PHYs: pcs_misc (optional) -> 3.
2046 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2047 if (IS_ERR(qmp->tx))
2048 return PTR_ERR(qmp->tx);
2050 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2051 if (IS_ERR(qmp->rx))
2052 return PTR_ERR(qmp->rx);
2054 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
2055 if (IS_ERR(qmp->pcs))
2056 return PTR_ERR(qmp->pcs);
2058 if (cfg->lanes >= 2) {
2059 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2060 if (IS_ERR(qmp->tx2))
2061 return PTR_ERR(qmp->tx2);
2063 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2064 if (IS_ERR(qmp->rx2))
2065 return PTR_ERR(qmp->rx2);
2067 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2069 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2072 if (IS_ERR(qmp->pcs_misc))
2073 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2080 struct platform_device *pdev = to_platform_device(qmp->dev);
2081 const struct qmp_phy_cfg *cfg = qmp->cfg;
2082 const struct qmp_ufs_offsets *offs = cfg->offsets;
2086 return -EINVAL;
2092 qmp->serdes = base + offs->serdes;
2093 qmp->pcs = base + offs->pcs;
2094 qmp->tx = base + offs->tx;
2095 qmp->rx = base + offs->rx;
2097 if (cfg->lanes >= 2) {
2098 qmp->tx2 = base + offs->tx2;
2099 qmp->rx2 = base + offs->rx2;
2107 struct device *dev = &pdev->dev;
2115 return -ENOMEM;
2117 qmp->dev = dev;
2119 qmp->cfg = of_device_get_match_data(dev);
2120 if (!qmp->cfg)
2121 return -EINVAL;
2132 np = of_get_next_available_child(dev->of_node, NULL);
2136 np = of_node_get(dev->of_node);
2146 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
2147 if (IS_ERR(qmp->phy)) {
2148 ret = PTR_ERR(qmp->phy);
2153 phy_set_drvdata(qmp->phy, qmp);
2168 .compatible = "qcom,msm8996-qmp-ufs-phy",
2171 .compatible = "qcom,msm8998-qmp-ufs-phy",
2174 .compatible = "qcom,sa8775p-qmp-ufs-phy",
2177 .compatible = "qcom,sc7180-qmp-ufs-phy",
2180 .compatible = "qcom,sc7280-qmp-ufs-phy",
2183 .compatible = "qcom,sc8180x-qmp-ufs-phy",
2186 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
2189 .compatible = "qcom,sdm845-qmp-ufs-phy",
2192 .compatible = "qcom,sm6115-qmp-ufs-phy",
2195 .compatible = "qcom,sm6125-qmp-ufs-phy",
2198 .compatible = "qcom,sm6350-qmp-ufs-phy",
2201 .compatible = "qcom,sm7150-qmp-ufs-phy",
2204 .compatible = "qcom,sm8150-qmp-ufs-phy",
2207 .compatible = "qcom,sm8250-qmp-ufs-phy",
2210 .compatible = "qcom,sm8350-qmp-ufs-phy",
2213 .compatible = "qcom,sm8450-qmp-ufs-phy",
2216 .compatible = "qcom,sm8475-qmp-ufs-phy",
2219 .compatible = "qcom,sm8550-qmp-ufs-phy",
2222 .compatible = "qcom,sm8650-qmp-ufs-phy",
2225 .compatible = "qcom,sm8750-qmp-ufs-phy",
2236 .name = "qcom-qmp-ufs-phy",