Lines Matching +full:sa8775p +full:- +full:gcc
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38 #include "phy-qcom-qmp-pcs-v6_30.h"
39 #include "phy-qcom-qmp-pcie-qhp.h"
43 /* set of registers with offsets different per-PHY */
3099 /* struct qmp_phy_cfg - per-PHY initialization config */
3105 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
3218 "vdda-phy", "vdda-pll",
3222 "vdda-phy", "vdda-pll", "vdda-qref",
4417 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_port_b()
4418 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_init_port_b()
4421 serdes = qmp->port_b + offs->serdes; in qmp_pcie_init_port_b()
4422 tx3 = qmp->port_b + offs->tx; in qmp_pcie_init_port_b()
4423 rx3 = qmp->port_b + offs->rx; in qmp_pcie_init_port_b()
4424 tx4 = qmp->port_b + offs->tx2; in qmp_pcie_init_port_b()
4425 rx4 = qmp->port_b + offs->rx2; in qmp_pcie_init_port_b()
4426 pcs = qmp->port_b + offs->pcs; in qmp_pcie_init_port_b()
4427 pcs_misc = qmp->port_b + offs->pcs_misc; in qmp_pcie_init_port_b()
4428 ln_shrd = qmp->port_b + offs->ln_shrd; in qmp_pcie_init_port_b()
4430 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_port_b()
4431 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); in qmp_pcie_init_port_b()
4433 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_port_b()
4434 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_port_b()
4436 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_port_b()
4437 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_port_b()
4439 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_port_b()
4440 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_port_b()
4442 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_port_b()
4447 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_registers()
4448 void __iomem *serdes = qmp->serdes; in qmp_pcie_init_registers()
4449 void __iomem *tx = qmp->tx; in qmp_pcie_init_registers()
4450 void __iomem *rx = qmp->rx; in qmp_pcie_init_registers()
4451 void __iomem *tx2 = qmp->tx2; in qmp_pcie_init_registers()
4452 void __iomem *rx2 = qmp->rx2; in qmp_pcie_init_registers()
4453 void __iomem *pcs = qmp->pcs; in qmp_pcie_init_registers()
4454 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_pcie_init_registers()
4455 void __iomem *pcs_lane1 = qmp->pcs_lane1; in qmp_pcie_init_registers()
4456 void __iomem *ln_shrd = qmp->ln_shrd; in qmp_pcie_init_registers()
4461 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_registers()
4467 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); in qmp_pcie_init_registers()
4468 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); in qmp_pcie_init_registers()
4470 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_registers()
4471 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_registers()
4473 if (cfg->lanes >= 2) { in qmp_pcie_init_registers()
4474 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_registers()
4475 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_registers()
4478 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_registers()
4479 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_registers()
4480 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); in qmp_pcie_init_registers()
4482 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_init_registers()
4483 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, in qmp_pcie_init_registers()
4484 cfg->serdes_4ln_num); in qmp_pcie_init_registers()
4488 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_registers()
4494 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init()
4495 void __iomem *pcs = qmp->pcs; in qmp_pcie_init()
4507 qmp->skip_init = qmp->nocsr_reset && in qmp_pcie_init()
4508 qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) && in qmp_pcie_init()
4509 qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); in qmp_pcie_init()
4511 if (!qmp->skip_init && !cfg->tbls.serdes_num) { in qmp_pcie_init()
4512 dev_err(qmp->dev, "Init sequence not available\n"); in qmp_pcie_init()
4513 return -ENODATA; in qmp_pcie_init()
4516 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
4518 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
4526 if (!qmp->skip_init) { in qmp_pcie_init()
4527 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4529 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
4534 ret = reset_control_assert(qmp->nocsr_reset); in qmp_pcie_init()
4536 dev_err(qmp->dev, "no-csr reset assert failed\n"); in qmp_pcie_init()
4542 if (!qmp->skip_init) { in qmp_pcie_init()
4543 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4545 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
4550 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_init()
4557 if (!qmp->skip_init) in qmp_pcie_init()
4558 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4560 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
4568 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_exit()
4570 if (qmp->nocsr_reset) in qmp_pcie_exit()
4571 reset_control_assert(qmp->nocsr_reset); in qmp_pcie_exit()
4573 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
4575 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_exit()
4577 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
4585 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_on()
4587 void __iomem *pcs = qmp->pcs; in qmp_pcie_power_on()
4596 if (qmp->skip_init) in qmp_pcie_power_on()
4599 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_on()
4600 cfg->pwrdn_ctrl); in qmp_pcie_power_on()
4602 if (qmp->mode == PHY_MODE_PCIE_RC) in qmp_pcie_power_on()
4603 mode_tbls = cfg->tbls_rc; in qmp_pcie_power_on()
4605 mode_tbls = cfg->tbls_ep; in qmp_pcie_power_on()
4607 qmp_pcie_init_registers(qmp, &cfg->tbls); in qmp_pcie_power_on()
4611 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
4615 ret = reset_control_deassert(qmp->nocsr_reset); in qmp_pcie_power_on()
4617 dev_err(qmp->dev, "no-csr reset deassert failed\n"); in qmp_pcie_power_on()
4621 if (qmp->skip_init) in qmp_pcie_power_on()
4625 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
4627 /* start SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_on()
4628 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_pcie_power_on()
4630 if (!cfg->skip_start_delay) in qmp_pcie_power_on()
4634 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_pcie_power_on()
4635 mask = cfg->phy_status; in qmp_pcie_power_on()
4639 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
4646 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
4654 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_off()
4656 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_off()
4659 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In in qmp_pcie_power_off()
4664 if (qmp->nocsr_reset) in qmp_pcie_power_off()
4668 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
4670 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_off()
4671 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_power_off()
4675 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
4676 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
4715 qmp->mode = submode; in qmp_pcie_set_mode()
4718 dev_err(&phy->dev, "Unsupported submode %d\n", submode); in qmp_pcie_set_mode()
4719 return -EINVAL; in qmp_pcie_set_mode()
4734 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_vreg_init()
4735 struct device *dev = qmp->dev; in qmp_pcie_vreg_init()
4736 int num = cfg->num_vregs; in qmp_pcie_vreg_init()
4739 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
4740 if (!qmp->vregs) in qmp_pcie_vreg_init()
4741 return -ENOMEM; in qmp_pcie_vreg_init()
4744 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
4746 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
4751 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_reset_init()
4752 struct device *dev = qmp->dev; in qmp_pcie_reset_init()
4756 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
4757 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
4758 if (!qmp->resets) in qmp_pcie_reset_init()
4759 return -ENOMEM; in qmp_pcie_reset_init()
4761 for (i = 0; i < cfg->num_resets; i++) in qmp_pcie_reset_init()
4762 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
4764 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
4768 qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr"); in qmp_pcie_reset_init()
4769 if (IS_ERR(qmp->nocsr_reset)) in qmp_pcie_reset_init()
4770 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), in qmp_pcie_reset_init()
4771 "failed to get no-csr reset\n"); in qmp_pcie_reset_init()
4778 struct device *dev = qmp->dev; in qmp_pcie_clk_init()
4782 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
4783 if (!qmp->clks) in qmp_pcie_clk_init()
4784 return -ENOMEM; in qmp_pcie_clk_init()
4787 qmp->clks[i].id = qmp_pciephy_clk_l[i]; in qmp_pcie_clk_init()
4789 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_pcie_clk_init()
4800 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4801 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4803 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4807 * +---------------+
4808 * | PHY block |<<---------------------------------------+
4810 * | +-------+ | +-----+ |
4811 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4812 * clk | +-------+ | +-----+
4813 * +---------------+
4817 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
4821 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); in phy_pipe_clk_register()
4823 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
4830 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
4833 if (qmp->cfg->pipe_clock_rate) in phy_pipe_clk_register()
4834 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; in phy_pipe_clk_register()
4836 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
4838 fixed->hw.init = &init; in phy_pipe_clk_register()
4840 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
4846 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
4847 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested
4849 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care
4853 * +---------------+
4854 * | PHY block |<<---------------------------------------------+
4856 * | +-------+ | +-----+ |
4857 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4858 * clk | +-------+ | +-----+
4859 * +---------------+
4863 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; in phy_aux_clk_register()
4867 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); in phy_aux_clk_register()
4872 fixed->fixed_rate = qmp->cfg->aux_clock_rate; in phy_aux_clk_register()
4873 fixed->hw.init = &init; in phy_aux_clk_register()
4875 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_aux_clk_register()
4883 if (!clkspec->args_count) in qmp_pcie_clk_hw_get()
4884 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4886 switch (clkspec->args[0]) { in qmp_pcie_clk_hw_get()
4888 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4890 return &qmp->aux_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4893 return ERR_PTR(-EINVAL); in qmp_pcie_clk_hw_get()
4904 if (qmp->cfg->aux_clock_rate) { in qmp_pcie_register_clocks()
4913 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); in qmp_pcie_register_clocks()
4922 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in qmp_pcie_register_clocks()
4927 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt_legacy()
4928 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt_legacy()
4929 struct device *dev = qmp->dev; in qmp_pcie_parse_dt_legacy()
4932 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_pcie_parse_dt_legacy()
4933 if (IS_ERR(qmp->serdes)) in qmp_pcie_parse_dt_legacy()
4934 return PTR_ERR(qmp->serdes); in qmp_pcie_parse_dt_legacy()
4938 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_pcie_parse_dt_legacy()
4939 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_pcie_parse_dt_legacy()
4940 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_pcie_parse_dt_legacy()
4942 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_parse_dt_legacy()
4943 if (IS_ERR(qmp->tx)) in qmp_pcie_parse_dt_legacy()
4944 return PTR_ERR(qmp->tx); in qmp_pcie_parse_dt_legacy()
4946 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4947 qmp->rx = qmp->tx; in qmp_pcie_parse_dt_legacy()
4949 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_parse_dt_legacy()
4950 if (IS_ERR(qmp->rx)) in qmp_pcie_parse_dt_legacy()
4951 return PTR_ERR(qmp->rx); in qmp_pcie_parse_dt_legacy()
4953 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_parse_dt_legacy()
4954 if (IS_ERR(qmp->pcs)) in qmp_pcie_parse_dt_legacy()
4955 return PTR_ERR(qmp->pcs); in qmp_pcie_parse_dt_legacy()
4957 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt_legacy()
4958 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4959 if (IS_ERR(qmp->tx2)) in qmp_pcie_parse_dt_legacy()
4960 return PTR_ERR(qmp->tx2); in qmp_pcie_parse_dt_legacy()
4962 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_parse_dt_legacy()
4963 if (IS_ERR(qmp->rx2)) in qmp_pcie_parse_dt_legacy()
4964 return PTR_ERR(qmp->rx2); in qmp_pcie_parse_dt_legacy()
4966 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_parse_dt_legacy()
4968 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4971 if (IS_ERR(qmp->pcs_misc) && in qmp_pcie_parse_dt_legacy()
4972 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4973 qmp->pcs_misc = qmp->pcs + 0x400; in qmp_pcie_parse_dt_legacy()
4975 if (IS_ERR(qmp->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4976 if (cfg->tbls.pcs_misc || in qmp_pcie_parse_dt_legacy()
4977 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || in qmp_pcie_parse_dt_legacy()
4978 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4979 return PTR_ERR(qmp->pcs_misc); in qmp_pcie_parse_dt_legacy()
4987 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) in qmp_pcie_parse_dt_legacy()
4988 qmp->pcs_lane1 = qmp->pcs_misc + in qmp_pcie_parse_dt_legacy()
4989 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); in qmp_pcie_parse_dt_legacy()
4997 qmp->num_pipe_clks = 1; in qmp_pcie_parse_dt_legacy()
4998 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt_legacy()
4999 qmp->pipe_clks[0].clk = clk; in qmp_pcie_parse_dt_legacy()
5010 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, in qmp_pcie_get_4ln_config()
5011 "qcom,4ln-config-sel", in qmp_pcie_get_4ln_config()
5015 if (ret == -ENOENT) in qmp_pcie_get_4ln_config()
5018 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); in qmp_pcie_get_4ln_config()
5024 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); in qmp_pcie_get_4ln_config()
5028 qmp->tcsr_4ln_config = ret; in qmp_pcie_get_4ln_config()
5030 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); in qmp_pcie_get_4ln_config()
5037 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt()
5038 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt()
5039 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_parse_dt()
5040 struct device *dev = qmp->dev; in qmp_pcie_parse_dt()
5045 return -EINVAL; in qmp_pcie_parse_dt()
5055 qmp->serdes = base + offs->serdes; in qmp_pcie_parse_dt()
5056 qmp->pcs = base + offs->pcs; in qmp_pcie_parse_dt()
5057 qmp->pcs_misc = base + offs->pcs_misc; in qmp_pcie_parse_dt()
5058 qmp->pcs_lane1 = base + offs->pcs_lane1; in qmp_pcie_parse_dt()
5059 qmp->tx = base + offs->tx; in qmp_pcie_parse_dt()
5060 qmp->rx = base + offs->rx; in qmp_pcie_parse_dt()
5062 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt()
5063 qmp->tx2 = base + offs->tx2; in qmp_pcie_parse_dt()
5064 qmp->rx2 = base + offs->rx2; in qmp_pcie_parse_dt()
5067 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_parse_dt()
5068 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); in qmp_pcie_parse_dt()
5069 if (IS_ERR(qmp->port_b)) in qmp_pcie_parse_dt()
5070 return PTR_ERR(qmp->port_b); in qmp_pcie_parse_dt()
5073 qmp->txz = base + offs->txz; in qmp_pcie_parse_dt()
5074 qmp->rxz = base + offs->rxz; in qmp_pcie_parse_dt()
5076 if (cfg->tbls.ln_shrd) in qmp_pcie_parse_dt()
5077 qmp->ln_shrd = base + offs->ln_shrd; in qmp_pcie_parse_dt()
5079 qmp->num_pipe_clks = 2; in qmp_pcie_parse_dt()
5080 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt()
5081 qmp->pipe_clks[1].id = "pipediv2"; in qmp_pcie_parse_dt()
5083 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); in qmp_pcie_parse_dt()
5087 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); in qmp_pcie_parse_dt()
5096 struct device *dev = &pdev->dev; in qmp_pcie_probe()
5104 return -ENOMEM; in qmp_pcie_probe()
5106 qmp->dev = dev; in qmp_pcie_probe()
5108 qmp->cfg = of_device_get_match_data(dev); in qmp_pcie_probe()
5109 if (!qmp->cfg) in qmp_pcie_probe()
5110 return -EINVAL; in qmp_pcie_probe()
5112 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); in qmp_pcie_probe()
5113 WARN_ON_ONCE(!qmp->cfg->phy_status); in qmp_pcie_probe()
5128 np = of_get_next_available_child(dev->of_node, NULL); in qmp_pcie_probe()
5132 np = of_node_get(dev->of_node); in qmp_pcie_probe()
5142 qmp->mode = PHY_MODE_PCIE_RC; in qmp_pcie_probe()
5144 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); in qmp_pcie_probe()
5145 if (IS_ERR(qmp->phy)) { in qmp_pcie_probe()
5146 ret = PTR_ERR(qmp->phy); in qmp_pcie_probe()
5151 phy_set_drvdata(qmp->phy, qmp); in qmp_pcie_probe()
5166 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5169 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
5172 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5175 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
5178 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
5181 .compatible = "qcom,msm8998-qmp-pcie-phy",
5184 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
5187 .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
5190 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
5193 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
5196 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
5199 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5202 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
5205 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
5208 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
5211 .compatible = "qcom,sdm845-qhp-pcie-phy",
5214 .compatible = "qcom,sdm845-qmp-pcie-phy",
5217 .compatible = "qcom,sdx55-qmp-pcie-phy",
5220 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
5223 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
5226 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
5229 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5232 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5235 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5238 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
5241 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
5244 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
5247 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
5250 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
5253 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
5256 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
5259 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
5262 .compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy",
5265 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
5268 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
5271 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
5274 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
5277 .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
5287 .name = "qcom-qmp-pcie-phy",