25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38 #include "phy-qcom-qmp-pcs-v6_30.h"
39 #include "phy-qcom-qmp-pcie-qhp.h"
3024 	/* QMP PHY pipe clock interface rate */
3027 	/* QMP PHY AUX clock interface rate */
4254 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)  in qmp_pcie_init_port_b()  argument
4256 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_init_port_b()
4260 	serdes = qmp->port_b + offs->serdes;  in qmp_pcie_init_port_b()
4261 	tx3 = qmp->port_b + offs->tx;  in qmp_pcie_init_port_b()
4262 	rx3 = qmp->port_b + offs->rx;  in qmp_pcie_init_port_b()
4263 	tx4 = qmp->port_b + offs->tx2;  in qmp_pcie_init_port_b()
4264 	rx4 = qmp->port_b + offs->rx2;  in qmp_pcie_init_port_b()
4265 	pcs = qmp->port_b + offs->pcs;  in qmp_pcie_init_port_b()
4266 	pcs_misc = qmp->port_b + offs->pcs_misc;  in qmp_pcie_init_port_b()
4267 	ln_shrd = qmp->port_b + offs->ln_shrd;  in qmp_pcie_init_port_b()
4269 	qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);  in qmp_pcie_init_port_b()
4270 	qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);  in qmp_pcie_init_port_b()
4272 	qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1);  in qmp_pcie_init_port_b()
4273 	qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1);  in qmp_pcie_init_port_b()
4275 	qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2);  in qmp_pcie_init_port_b()
4276 	qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2);  in qmp_pcie_init_port_b()
4278 	qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);  in qmp_pcie_init_port_b()
4279 	qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);  in qmp_pcie_init_port_b()
4281 	qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);  in qmp_pcie_init_port_b()
4284 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)  in qmp_pcie_init_registers()  argument
4286 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_init_registers()
4287 	void __iomem *serdes = qmp->serdes;  in qmp_pcie_init_registers()
4288 	void __iomem *tx = qmp->tx;  in qmp_pcie_init_registers()
4289 	void __iomem *rx = qmp->rx;  in qmp_pcie_init_registers()
4290 	void __iomem *tx2 = qmp->tx2;  in qmp_pcie_init_registers()
4291 	void __iomem *rx2 = qmp->rx2;  in qmp_pcie_init_registers()
4292 	void __iomem *pcs = qmp->pcs;  in qmp_pcie_init_registers()
4293 	void __iomem *pcs_misc = qmp->pcs_misc;  in qmp_pcie_init_registers()
4294 	void __iomem *pcs_lane1 = qmp->pcs_lane1;  in qmp_pcie_init_registers()
4295 	void __iomem *ln_shrd = qmp->ln_shrd;  in qmp_pcie_init_registers()
4300 	qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);  in qmp_pcie_init_registers()
4306 	qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num);  in qmp_pcie_init_registers()
4307 	qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num);  in qmp_pcie_init_registers()
4309 	qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);  in qmp_pcie_init_registers()
4310 	qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);  in qmp_pcie_init_registers()
4313 		qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2);  in qmp_pcie_init_registers()
4314 		qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2);  in qmp_pcie_init_registers()
4317 	qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);  in qmp_pcie_init_registers()
4318 	qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);  in qmp_pcie_init_registers()
4319 	qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);  in qmp_pcie_init_registers()
4321 	if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {  in qmp_pcie_init_registers()
4322 		qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,  in qmp_pcie_init_registers()
4324 		qmp_pcie_init_port_b(qmp, tbls);  in qmp_pcie_init_registers()
4327 	qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);  in qmp_pcie_init_registers()
4332 	struct qmp_pcie *qmp = phy_get_drvdata(phy);  in qmp_pcie_init()  local
4333 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_init()
4334 	void __iomem *pcs = qmp->pcs;  in qmp_pcie_init()
4338 	qmp->skip_init = qmp->nocsr_reset && phy_initialized;  in qmp_pcie_init()
4345 	if (!qmp->skip_init && !cfg->tbls.serdes_num) {  in qmp_pcie_init()
4346 		dev_err(qmp->dev, "Init sequence not available\n");  in qmp_pcie_init()
4350 	ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);  in qmp_pcie_init()
4352 		dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);  in qmp_pcie_init()
4360 	if (!qmp->skip_init) {  in qmp_pcie_init()
4361 		ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);  in qmp_pcie_init()
4363 			dev_err(qmp->dev, "reset assert failed\n");  in qmp_pcie_init()
4368 	ret = reset_control_assert(qmp->nocsr_reset);  in qmp_pcie_init()
4370 		dev_err(qmp->dev, "no-csr reset assert failed\n");  in qmp_pcie_init()
4376 	if (!qmp->skip_init) {  in qmp_pcie_init()
4377 		ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);  in qmp_pcie_init()
4379 			dev_err(qmp->dev, "reset deassert failed\n");  in qmp_pcie_init()
4384 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);  in qmp_pcie_init()
4391 	if (!qmp->skip_init)  in qmp_pcie_init()
4392 		reset_control_bulk_assert(cfg->num_resets, qmp->resets);  in qmp_pcie_init()
4394 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);  in qmp_pcie_init()
4401 	struct qmp_pcie *qmp = phy_get_drvdata(phy);  in qmp_pcie_exit()  local
4402 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_exit()
4404 	if (qmp->nocsr_reset)  in qmp_pcie_exit()
4405 		reset_control_assert(qmp->nocsr_reset);  in qmp_pcie_exit()
4407 		reset_control_bulk_assert(cfg->num_resets, qmp->resets);  in qmp_pcie_exit()
4409 	clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);  in qmp_pcie_exit()
4411 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);  in qmp_pcie_exit()
4418 	struct qmp_pcie *qmp = phy_get_drvdata(phy);  in qmp_pcie_power_on()  local
4419 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_power_on()
4421 	void __iomem *pcs = qmp->pcs;  in qmp_pcie_power_on()
4430 	if (qmp->skip_init)  in qmp_pcie_power_on()
4436 	if (qmp->mode == PHY_MODE_PCIE_RC)  in qmp_pcie_power_on()
4441 	qmp_pcie_init_registers(qmp, &cfg->tbls);  in qmp_pcie_power_on()
4442 	qmp_pcie_init_registers(qmp, mode_tbls);  in qmp_pcie_power_on()
4445 	ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);  in qmp_pcie_power_on()
4449 	ret = reset_control_deassert(qmp->nocsr_reset);  in qmp_pcie_power_on()
4451 		dev_err(qmp->dev, "no-csr reset deassert failed\n");  in qmp_pcie_power_on()
4455 	if (qmp->skip_init)  in qmp_pcie_power_on()
4473 		dev_err(qmp->dev, "phy initialization timed-out\n");  in qmp_pcie_power_on()
4480 	clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);  in qmp_pcie_power_on()
4487 	struct qmp_pcie *qmp = phy_get_drvdata(phy);  in qmp_pcie_power_off()  local
4488 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_power_off()
4490 	clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);  in qmp_pcie_power_off()
4493 	 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In  in qmp_pcie_power_off()
4498 	if (qmp->nocsr_reset)  in qmp_pcie_power_off()
4502 	qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);  in qmp_pcie_power_off()
4505 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],  in qmp_pcie_power_off()
4509 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],  in qmp_pcie_power_off()
4544 	struct qmp_pcie *qmp = phy_get_drvdata(phy);  in qmp_pcie_set_mode()  local
4549 		qmp->mode = submode;  in qmp_pcie_set_mode()
4566 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)  in qmp_pcie_vreg_init()  argument
4568 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_vreg_init()
4569 	struct device *dev = qmp->dev;  in qmp_pcie_vreg_init()
4573 	qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);  in qmp_pcie_vreg_init()
4574 	if (!qmp->vregs)  in qmp_pcie_vreg_init()
4578 		qmp->vregs[i].supply = cfg->vreg_list[i];  in qmp_pcie_vreg_init()
4580 	return devm_regulator_bulk_get(dev, num, qmp->vregs);  in qmp_pcie_vreg_init()
4583 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)  in qmp_pcie_reset_init()  argument
4585 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_reset_init()
4586 	struct device *dev = qmp->dev;  in qmp_pcie_reset_init()
4590 	qmp->resets = devm_kcalloc(dev, cfg->num_resets,  in qmp_pcie_reset_init()
4591 				   sizeof(*qmp->resets), GFP_KERNEL);  in qmp_pcie_reset_init()
4592 	if (!qmp->resets)  in qmp_pcie_reset_init()
4596 		qmp->resets[i].id = cfg->reset_list[i];  in qmp_pcie_reset_init()
4598 	ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);  in qmp_pcie_reset_init()
4602 	qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");  in qmp_pcie_reset_init()
4603 	if (IS_ERR(qmp->nocsr_reset))  in qmp_pcie_reset_init()
4604 		return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),  in qmp_pcie_reset_init()
4610 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)  in qmp_pcie_clk_init()  argument
4612 	struct device *dev = qmp->dev;  in qmp_pcie_clk_init()
4616 	qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);  in qmp_pcie_clk_init()
4617 	if (!qmp->clks)  in qmp_pcie_clk_init()
4621 		qmp->clks[i].id = qmp_pciephy_clk_l[i];  in qmp_pcie_clk_init()
4623 	return devm_clk_bulk_get_optional(dev, num, qmp->clks);  in qmp_pcie_clk_init()
4649 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)  in phy_pipe_clk_register()  argument
4651 	struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;  in phy_pipe_clk_register()
4657 		dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);  in phy_pipe_clk_register()
4664 	 * Controllers using QMP PHY-s use 125MHz pipe clock interface  in phy_pipe_clk_register()
4667 	if (qmp->cfg->pipe_clock_rate)  in phy_pipe_clk_register()
4668 		fixed->fixed_rate = qmp->cfg->pipe_clock_rate;  in phy_pipe_clk_register()
4674 	return devm_clk_hw_register(qmp->dev, &fixed->hw);  in phy_pipe_clk_register()
4695 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)  in phy_aux_clk_register()  argument
4697 	struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;  in phy_aux_clk_register()
4701 	snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));  in phy_aux_clk_register()
4706 	fixed->fixed_rate = qmp->cfg->aux_clock_rate;  in phy_aux_clk_register()
4709 	return devm_clk_hw_register(qmp->dev, &fixed->hw);  in phy_aux_clk_register()
4714 	struct qmp_pcie *qmp = data;  in qmp_pcie_clk_hw_get()  local
4718 		return &qmp->pipe_clk_fixed.hw;  in qmp_pcie_clk_hw_get()
4722 		return &qmp->pipe_clk_fixed.hw;  in qmp_pcie_clk_hw_get()
4724 		return &qmp->aux_clk_fixed.hw;  in qmp_pcie_clk_hw_get()
4730 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)  in qmp_pcie_register_clocks()  argument
4734 	ret = phy_pipe_clk_register(qmp, np);  in qmp_pcie_register_clocks()
4738 	if (qmp->cfg->aux_clock_rate) {  in qmp_pcie_register_clocks()
4739 		ret = phy_aux_clk_register(qmp, np);  in qmp_pcie_register_clocks()
4743 		ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp);  in qmp_pcie_register_clocks()
4747 		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);  in qmp_pcie_register_clocks()
4756 	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);  in qmp_pcie_register_clocks()
4759 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)  in qmp_pcie_parse_dt_legacy()  argument
4761 	struct platform_device *pdev = to_platform_device(qmp->dev);  in qmp_pcie_parse_dt_legacy()
4762 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_parse_dt_legacy()
4763 	struct device *dev = qmp->dev;  in qmp_pcie_parse_dt_legacy()
4766 	qmp->serdes = devm_platform_ioremap_resource(pdev, 0);  in qmp_pcie_parse_dt_legacy()
4767 	if (IS_ERR(qmp->serdes))  in qmp_pcie_parse_dt_legacy()
4768 		return PTR_ERR(qmp->serdes);  in qmp_pcie_parse_dt_legacy()
4776 	qmp->tx = devm_of_iomap(dev, np, 0, NULL);  in qmp_pcie_parse_dt_legacy()
4777 	if (IS_ERR(qmp->tx))  in qmp_pcie_parse_dt_legacy()
4778 		return PTR_ERR(qmp->tx);  in qmp_pcie_parse_dt_legacy()
4781 		qmp->rx = qmp->tx;  in qmp_pcie_parse_dt_legacy()
4783 		qmp->rx = devm_of_iomap(dev, np, 1, NULL);  in qmp_pcie_parse_dt_legacy()
4784 	if (IS_ERR(qmp->rx))  in qmp_pcie_parse_dt_legacy()
4785 		return PTR_ERR(qmp->rx);  in qmp_pcie_parse_dt_legacy()
4787 	qmp->pcs = devm_of_iomap(dev, np, 2, NULL);  in qmp_pcie_parse_dt_legacy()
4788 	if (IS_ERR(qmp->pcs))  in qmp_pcie_parse_dt_legacy()
4789 		return PTR_ERR(qmp->pcs);  in qmp_pcie_parse_dt_legacy()
4792 		qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);  in qmp_pcie_parse_dt_legacy()
4793 		if (IS_ERR(qmp->tx2))  in qmp_pcie_parse_dt_legacy()
4794 			return PTR_ERR(qmp->tx2);  in qmp_pcie_parse_dt_legacy()
4796 		qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);  in qmp_pcie_parse_dt_legacy()
4797 		if (IS_ERR(qmp->rx2))  in qmp_pcie_parse_dt_legacy()
4798 			return PTR_ERR(qmp->rx2);  in qmp_pcie_parse_dt_legacy()
4800 		qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);  in qmp_pcie_parse_dt_legacy()
4802 		qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);  in qmp_pcie_parse_dt_legacy()
4805 	if (IS_ERR(qmp->pcs_misc) &&  in qmp_pcie_parse_dt_legacy()
4806 	    of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))  in qmp_pcie_parse_dt_legacy()
4807 		qmp->pcs_misc = qmp->pcs + 0x400;  in qmp_pcie_parse_dt_legacy()
4809 	if (IS_ERR(qmp->pcs_misc)) {  in qmp_pcie_parse_dt_legacy()
4813 			return PTR_ERR(qmp->pcs_misc);  in qmp_pcie_parse_dt_legacy()
4821 	if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0)  in qmp_pcie_parse_dt_legacy()
4822 		qmp->pcs_lane1 = qmp->pcs_misc +  in qmp_pcie_parse_dt_legacy()
4831 	qmp->num_pipe_clks = 1;  in qmp_pcie_parse_dt_legacy()
4832 	qmp->pipe_clks[0].id = "pipe";  in qmp_pcie_parse_dt_legacy()
4833 	qmp->pipe_clks[0].clk = clk;  in qmp_pcie_parse_dt_legacy()
4838 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)  in qmp_pcie_get_4ln_config()  argument
4844 	tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,  in qmp_pcie_get_4ln_config()
4852 		dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);  in qmp_pcie_get_4ln_config()
4858 		dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);  in qmp_pcie_get_4ln_config()
4862 	qmp->tcsr_4ln_config = ret;  in qmp_pcie_get_4ln_config()
4864 	dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);  in qmp_pcie_get_4ln_config()
4869 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)  in qmp_pcie_parse_dt()  argument
4871 	struct platform_device *pdev = to_platform_device(qmp->dev);  in qmp_pcie_parse_dt()
4872 	const struct qmp_phy_cfg *cfg = qmp->cfg;  in qmp_pcie_parse_dt()
4874 	struct device *dev = qmp->dev;  in qmp_pcie_parse_dt()
4881 	ret = qmp_pcie_get_4ln_config(qmp);  in qmp_pcie_parse_dt()
4889 	qmp->serdes = base + offs->serdes;  in qmp_pcie_parse_dt()
4890 	qmp->pcs = base + offs->pcs;  in qmp_pcie_parse_dt()
4891 	qmp->pcs_misc = base + offs->pcs_misc;  in qmp_pcie_parse_dt()
4892 	qmp->pcs_lane1 = base + offs->pcs_lane1;  in qmp_pcie_parse_dt()
4893 	qmp->tx = base + offs->tx;  in qmp_pcie_parse_dt()
4894 	qmp->rx = base + offs->rx;  in qmp_pcie_parse_dt()
4897 		qmp->tx2 = base + offs->tx2;  in qmp_pcie_parse_dt()
4898 		qmp->rx2 = base + offs->rx2;  in qmp_pcie_parse_dt()
4901 	if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {  in qmp_pcie_parse_dt()
4902 		qmp->port_b = devm_platform_ioremap_resource(pdev, 1);  in qmp_pcie_parse_dt()
4903 		if (IS_ERR(qmp->port_b))  in qmp_pcie_parse_dt()
4904 			return PTR_ERR(qmp->port_b);  in qmp_pcie_parse_dt()
4907 	qmp->txz = base + offs->txz;  in qmp_pcie_parse_dt()
4908 	qmp->rxz = base + offs->rxz;  in qmp_pcie_parse_dt()
4911 		qmp->ln_shrd = base + offs->ln_shrd;  in qmp_pcie_parse_dt()
4913 	qmp->num_pipe_clks = 2;  in qmp_pcie_parse_dt()
4914 	qmp->pipe_clks[0].id = "pipe";  in qmp_pcie_parse_dt()
4915 	qmp->pipe_clks[1].id = "pipediv2";  in qmp_pcie_parse_dt()
4917 	ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);  in qmp_pcie_parse_dt()
4921 	ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);  in qmp_pcie_parse_dt()
4933 	struct qmp_pcie *qmp;  in qmp_pcie_probe()  local
4936 	qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);  in qmp_pcie_probe()
4937 	if (!qmp)  in qmp_pcie_probe()
4940 	qmp->dev = dev;  in qmp_pcie_probe()
4942 	qmp->cfg = of_device_get_match_data(dev);  in qmp_pcie_probe()
4943 	if (!qmp->cfg)  in qmp_pcie_probe()
4946 	WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);  in qmp_pcie_probe()
4947 	WARN_ON_ONCE(!qmp->cfg->phy_status);  in qmp_pcie_probe()
4949 	ret = qmp_pcie_clk_init(qmp);  in qmp_pcie_probe()
4953 	ret = qmp_pcie_reset_init(qmp);  in qmp_pcie_probe()
4957 	ret = qmp_pcie_vreg_init(qmp);  in qmp_pcie_probe()
4964 		ret = qmp_pcie_parse_dt_legacy(qmp, np);  in qmp_pcie_probe()
4967 		ret = qmp_pcie_parse_dt(qmp);  in qmp_pcie_probe()
4972 	ret = qmp_pcie_register_clocks(qmp, np);  in qmp_pcie_probe()
4976 	qmp->mode = PHY_MODE_PCIE_RC;  in qmp_pcie_probe()
4978 	qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);  in qmp_pcie_probe()
4979 	if (IS_ERR(qmp->phy)) {  in qmp_pcie_probe()
4980 		ret = PTR_ERR(qmp->phy);  in qmp_pcie_probe()
4985 	phy_set_drvdata(qmp->phy, qmp);  in qmp_pcie_probe()
5000 		.compatible = "qcom,ipq6018-qmp-pcie-phy",
5003 		.compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
5006 		.compatible = "qcom,ipq8074-qmp-pcie-phy",
5009 		.compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
5012 		.compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
5015 		.compatible = "qcom,msm8998-qmp-pcie-phy",
5018 		.compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
5021 		.compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
5024 		.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
5027 		.compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
5030 		.compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
5033 		.compatible = "qcom,sc8180x-qmp-pcie-phy",
5036 		.compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
5039 		.compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
5042 		.compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
5048 		.compatible = "qcom,sdm845-qmp-pcie-phy",
5051 		.compatible = "qcom,sdx55-qmp-pcie-phy",
5054 		.compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
5057 		.compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
5060 		.compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
5063 		.compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5066 		.compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5069 		.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5072 		.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
5075 		.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
5078 		.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
5081 		.compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
5084 		.compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
5087 		.compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
5090 		.compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
5093 		.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
5096 		.compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
5099 		.compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
5102 		.compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
5105 		.compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
5108 		.compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
5118 		.name	= "qcom-qmp-pcie-phy",
5126 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");