Lines Matching +full:sm8750 +full:- +full:dp
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include <drm/bridge/aux-bridge.h>
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
28 #include "phy-qcom-qmp-common.h"
30 #include "phy-qcom-qmp.h"
31 #include "phy-qcom-qmp-pcs-misc-v3.h"
32 #include "phy-qcom-qmp-pcs-usb-v4.h"
33 #include "phy-qcom-qmp-pcs-usb-v5.h"
34 #include "phy-qcom-qmp-pcs-usb-v6.h"
35 #include "phy-qcom-qmp-pcs-usb-v8.h"
37 #include "phy-qcom-qmp-dp-com-v3.h"
39 #include "phy-qcom-qmp-dp-phy.h"
40 #include "phy-qcom-qmp-dp-phy-v3.h"
41 #include "phy-qcom-qmp-dp-phy-v4.h"
42 #include "phy-qcom-qmp-dp-phy-v5.h"
43 #include "phy-qcom-qmp-dp-phy-v6.h"
46 /* DP PHY soft reset */
48 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
57 #define DP_MODE BIT(1) /* enables DP mode */
65 /* set of registers with offsets different per-PHY */
1645 { .name = "vdda-phy", .enable_load = 21800 },
1646 { .name = "vdda-pll", .enable_load = 36000 },
1761 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1778 /* Init sequence for DP PHY block link rates */
1788 /* DP PHY swing and pre_emphasis tables */
1794 /* DP PHY callbacks */
2505 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_serdes_init()
2506 void __iomem *serdes = qmp->dp_serdes; in qmp_combo_dp_serdes_init()
2507 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_dp_serdes_init()
2509 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, in qmp_combo_dp_serdes_init()
2510 cfg->dp_serdes_tbl_num); in qmp_combo_dp_serdes_init()
2512 switch (dp_opts->link_rate) { in qmp_combo_dp_serdes_init()
2514 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, in qmp_combo_dp_serdes_init()
2515 cfg->serdes_tbl_rbr_num); in qmp_combo_dp_serdes_init()
2518 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, in qmp_combo_dp_serdes_init()
2519 cfg->serdes_tbl_hbr_num); in qmp_combo_dp_serdes_init()
2522 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, in qmp_combo_dp_serdes_init()
2523 cfg->serdes_tbl_hbr2_num); in qmp_combo_dp_serdes_init()
2526 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, in qmp_combo_dp_serdes_init()
2527 cfg->serdes_tbl_hbr3_num); in qmp_combo_dp_serdes_init()
2531 return -EINVAL; in qmp_combo_dp_serdes_init()
2539 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v3_dp_aux_init()
2543 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v3_dp_aux_init()
2548 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); in qmp_v3_dp_aux_init()
2550 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v3_dp_aux_init()
2556 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v3_dp_aux_init()
2562 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); in qmp_v3_dp_aux_init()
2564 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); in qmp_v3_dp_aux_init()
2565 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v3_dp_aux_init()
2566 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v3_dp_aux_init()
2567 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); in qmp_v3_dp_aux_init()
2568 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); in qmp_v3_dp_aux_init()
2569 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); in qmp_v3_dp_aux_init()
2570 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); in qmp_v3_dp_aux_init()
2571 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); in qmp_v3_dp_aux_init()
2572 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); in qmp_v3_dp_aux_init()
2573 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); in qmp_v3_dp_aux_init()
2574 qmp->dp_aux_cfg = 0; in qmp_v3_dp_aux_init()
2579 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); in qmp_v3_dp_aux_init()
2584 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_configure_dp_swing()
2585 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_configure_dp_swing()
2590 for (i = 0; i < dp_opts->lanes; i++) { in qmp_combo_configure_dp_swing()
2591 v_level = max(v_level, dp_opts->voltage[i]); in qmp_combo_configure_dp_swing()
2592 p_level = max(p_level, dp_opts->pre[i]); in qmp_combo_configure_dp_swing()
2595 if (dp_opts->link_rate <= 2700) { in qmp_combo_configure_dp_swing()
2596 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2597 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2599 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2600 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; in qmp_combo_configure_dp_swing()
2605 return -EINVAL; in qmp_combo_configure_dp_swing()
2611 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_combo_configure_dp_swing()
2612 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_combo_configure_dp_swing()
2613 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_combo_configure_dp_swing()
2614 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_combo_configure_dp_swing()
2621 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_v3_configure_dp_tx()
2627 if (dp_opts->lanes == 1) { in qmp_v3_configure_dp_tx()
2635 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qmp_v3_configure_dp_tx()
2636 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qmp_v3_configure_dp_tx()
2637 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); in qmp_v3_configure_dp_tx()
2638 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); in qmp_v3_configure_dp_tx()
2643 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); in qmp_combo_configure_dp_mode()
2644 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_configure_dp_mode()
2650 if (dp_opts->lanes == 4 || reverse) in qmp_combo_configure_dp_mode()
2652 if (dp_opts->lanes == 4 || !reverse) in qmp_combo_configure_dp_mode()
2655 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_combo_configure_dp_mode()
2658 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
2660 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); in qmp_combo_configure_dp_mode()
2667 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_combo_configure_dp_clocks()
2670 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_configure_dp_clocks()
2672 switch (dp_opts->link_rate) { in qmp_combo_configure_dp_clocks()
2691 return -EINVAL; in qmp_combo_configure_dp_clocks()
2693 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); in qmp_combo_configure_dp_clocks()
2695 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); in qmp_combo_configure_dp_clocks()
2696 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); in qmp_combo_configure_dp_clocks()
2703 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v3_configure_dp_phy()
2709 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); in qmp_v3_configure_dp_phy()
2710 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); in qmp_v3_configure_dp_phy()
2716 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v3_configure_dp_phy()
2717 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2718 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2719 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2720 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2722 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); in qmp_v3_configure_dp_phy()
2724 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], in qmp_v3_configure_dp_phy()
2729 return -ETIMEDOUT; in qmp_v3_configure_dp_phy()
2731 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2733 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v3_configure_dp_phy()
2738 return -ETIMEDOUT; in qmp_v3_configure_dp_phy()
2740 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2742 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v3_configure_dp_phy()
2744 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v3_configure_dp_phy()
2760 qmp->dp_aux_cfg++; in qmp_v3_calibrate_dp_phy()
2761 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qmp_v3_calibrate_dp_phy()
2762 val = cfg1_settings[qmp->dp_aux_cfg]; in qmp_v3_calibrate_dp_phy()
2764 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v3_calibrate_dp_phy()
2771 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v4_dp_aux_init()
2775 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_v4_dp_aux_init()
2778 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); in qmp_v4_dp_aux_init()
2780 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); in qmp_v4_dp_aux_init()
2781 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v4_dp_aux_init()
2782 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v4_dp_aux_init()
2783 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); in qmp_v4_dp_aux_init()
2784 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); in qmp_v4_dp_aux_init()
2785 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); in qmp_v4_dp_aux_init()
2786 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); in qmp_v4_dp_aux_init()
2787 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); in qmp_v4_dp_aux_init()
2788 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); in qmp_v4_dp_aux_init()
2789 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); in qmp_v4_dp_aux_init()
2790 qmp->dp_aux_cfg = 0; in qmp_v4_dp_aux_init()
2795 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); in qmp_v4_dp_aux_init()
2800 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v4_configure_dp_tx()
2803 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_tx()
2804 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_tx()
2806 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_tx()
2807 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_tx()
2814 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v456_configure_dp_phy()
2818 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); in qmp_v456_configure_dp_phy()
2822 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v456_configure_dp_phy()
2823 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); in qmp_v456_configure_dp_phy()
2825 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); in qmp_v456_configure_dp_phy()
2826 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); in qmp_v456_configure_dp_phy()
2832 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2833 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2834 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2835 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2837 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); in qmp_v456_configure_dp_phy()
2839 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], in qmp_v456_configure_dp_phy()
2844 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2846 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], in qmp_v456_configure_dp_phy()
2851 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2853 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], in qmp_v456_configure_dp_phy()
2858 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2860 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v456_configure_dp_phy()
2862 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v456_configure_dp_phy()
2867 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2869 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v456_configure_dp_phy()
2874 return -ETIMEDOUT; in qmp_v456_configure_dp_phy()
2881 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_v4_configure_dp_phy()
2882 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); in qmp_v4_configure_dp_phy()
2883 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; in qmp_v4_configure_dp_phy()
2893 * At least for 7nm DP PHY this has to be done after enabling link in qmp_v4_configure_dp_phy()
2897 if (dp_opts->lanes == 1) { in qmp_v4_configure_dp_phy()
2902 } else if (dp_opts->lanes == 2) { in qmp_v4_configure_dp_phy()
2914 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); in qmp_v4_configure_dp_phy()
2915 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); in qmp_v4_configure_dp_phy()
2916 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); in qmp_v4_configure_dp_phy()
2917 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); in qmp_v4_configure_dp_phy()
2919 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v4_configure_dp_phy()
2921 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); in qmp_v4_configure_dp_phy()
2923 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], in qmp_v4_configure_dp_phy()
2928 return -ETIMEDOUT; in qmp_v4_configure_dp_phy()
2930 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); in qmp_v4_configure_dp_phy()
2931 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); in qmp_v4_configure_dp_phy()
2933 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_phy()
2934 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); in qmp_v4_configure_dp_phy()
2936 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_phy()
2937 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); in qmp_v4_configure_dp_phy()
2951 qmp->dp_aux_cfg++; in qmp_v4_calibrate_dp_phy()
2952 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); in qmp_v4_calibrate_dp_phy()
2953 val = cfg1_settings[qmp->dp_aux_cfg]; in qmp_v4_calibrate_dp_phy()
2955 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); in qmp_v4_calibrate_dp_phy()
2962 const struct phy_configure_opts_dp *dp_opts = &opts->dp; in qmp_combo_dp_configure()
2964 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_configure()
2966 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_configure()
2968 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); in qmp_combo_dp_configure()
2969 if (qmp->dp_opts.set_voltages) { in qmp_combo_dp_configure()
2970 cfg->configure_dp_tx(qmp); in qmp_combo_dp_configure()
2971 qmp->dp_opts.set_voltages = 0; in qmp_combo_dp_configure()
2974 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_configure()
2982 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_calibrate()
2985 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_calibrate()
2987 if (cfg->calibrate_dp_phy) in qmp_combo_dp_calibrate()
2988 ret = cfg->calibrate_dp_phy(qmp); in qmp_combo_dp_calibrate()
2990 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_calibrate()
2997 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_com_init()
2998 void __iomem *com = qmp->com; in qmp_combo_com_init()
3002 if (!force && qmp->init_count++) in qmp_combo_com_init()
3005 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_init()
3007 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_combo_com_init()
3011 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
3013 dev_err(qmp->dev, "reset assert failed\n"); in qmp_combo_com_init()
3017 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
3019 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_combo_com_init()
3023 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); in qmp_combo_com_init()
3036 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) in qmp_combo_com_init()
3041 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ in qmp_combo_com_init()
3049 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_com_init()
3055 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_init()
3057 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_init()
3059 qmp->init_count--; in qmp_combo_com_init()
3066 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_com_exit()
3068 if (!force && --qmp->init_count) in qmp_combo_com_exit()
3071 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_combo_com_exit()
3073 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_combo_com_exit()
3075 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_combo_com_exit()
3083 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_init()
3086 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_init()
3092 cfg->dp_aux_init(qmp); in qmp_combo_dp_init()
3094 qmp->dp_init_count++; in qmp_combo_dp_init()
3097 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_init()
3105 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_exit()
3109 qmp->dp_init_count--; in qmp_combo_dp_exit()
3111 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_exit()
3119 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_dp_power_on()
3120 void __iomem *tx = qmp->dp_tx; in qmp_combo_dp_power_on()
3121 void __iomem *tx2 = qmp->dp_tx2; in qmp_combo_dp_power_on()
3123 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_power_on()
3127 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); in qmp_combo_dp_power_on()
3128 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); in qmp_combo_dp_power_on()
3130 /* Configure special DP tx tunings */ in qmp_combo_dp_power_on()
3131 cfg->configure_dp_tx(qmp); in qmp_combo_dp_power_on()
3134 cfg->configure_dp_phy(qmp); in qmp_combo_dp_power_on()
3136 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_power_on()
3145 mutex_lock(&qmp->phy_mutex); in qmp_combo_dp_power_off()
3147 /* Assert DP PHY power down */ in qmp_combo_dp_power_off()
3148 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); in qmp_combo_dp_power_off()
3150 mutex_unlock(&qmp->phy_mutex); in qmp_combo_dp_power_off()
3158 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_usb_power_on()
3159 void __iomem *serdes = qmp->serdes; in qmp_combo_usb_power_on()
3160 void __iomem *tx = qmp->tx; in qmp_combo_usb_power_on()
3161 void __iomem *rx = qmp->rx; in qmp_combo_usb_power_on()
3162 void __iomem *tx2 = qmp->tx2; in qmp_combo_usb_power_on()
3163 void __iomem *rx2 = qmp->rx2; in qmp_combo_usb_power_on()
3164 void __iomem *pcs = qmp->pcs; in qmp_combo_usb_power_on()
3165 void __iomem *pcs_usb = qmp->pcs_usb; in qmp_combo_usb_power_on()
3170 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); in qmp_combo_usb_power_on()
3172 ret = clk_prepare_enable(qmp->pipe_clk); in qmp_combo_usb_power_on()
3174 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); in qmp_combo_usb_power_on()
3179 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); in qmp_combo_usb_power_on()
3180 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); in qmp_combo_usb_power_on()
3182 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); in qmp_combo_usb_power_on()
3183 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); in qmp_combo_usb_power_on()
3185 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qmp_combo_usb_power_on()
3188 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, in qmp_combo_usb_power_on()
3189 cfg->pcs_usb_tbl_num); in qmp_combo_usb_power_on()
3191 if (cfg->has_pwrdn_delay) in qmp_combo_usb_power_on()
3195 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_on()
3197 /* start SerDes and Phy-Coding-Sublayer */ in qmp_combo_usb_power_on()
3198 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_combo_usb_power_on()
3200 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_combo_usb_power_on()
3204 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_combo_usb_power_on()
3211 clk_disable_unprepare(qmp->pipe_clk); in qmp_combo_usb_power_on()
3219 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_usb_power_off()
3221 clk_disable_unprepare(qmp->pipe_clk); in qmp_combo_usb_power_off()
3224 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_combo_usb_power_off()
3226 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_combo_usb_power_off()
3227 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_combo_usb_power_off()
3231 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_combo_usb_power_off()
3242 mutex_lock(&qmp->phy_mutex); in qmp_combo_usb_init()
3253 qmp->usb_init_count++; in qmp_combo_usb_init()
3256 mutex_unlock(&qmp->phy_mutex); in qmp_combo_usb_init()
3265 mutex_lock(&qmp->phy_mutex); in qmp_combo_usb_exit()
3274 qmp->usb_init_count--; in qmp_combo_usb_exit()
3277 mutex_unlock(&qmp->phy_mutex); in qmp_combo_usb_exit()
3285 qmp->mode = mode; in qmp_combo_usb_set_mode()
3309 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_enable_autonomous_mode()
3310 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; in qmp_combo_enable_autonomous_mode()
3311 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_combo_enable_autonomous_mode()
3314 if (qmp->mode == PHY_MODE_USB_HOST_SS || in qmp_combo_enable_autonomous_mode()
3315 qmp->mode == PHY_MODE_USB_DEVICE_SS) in qmp_combo_enable_autonomous_mode()
3321 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_enable_autonomous_mode()
3323 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_enable_autonomous_mode()
3325 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qmp_combo_enable_autonomous_mode()
3329 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); in qmp_combo_enable_autonomous_mode()
3338 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_disable_autonomous_mode()
3339 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; in qmp_combo_disable_autonomous_mode()
3340 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_combo_disable_autonomous_mode()
3346 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qmp_combo_disable_autonomous_mode()
3349 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_disable_autonomous_mode()
3351 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qmp_combo_disable_autonomous_mode()
3358 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); in qmp_combo_runtime_suspend()
3360 if (!qmp->init_count) { in qmp_combo_runtime_suspend()
3367 clk_disable_unprepare(qmp->pipe_clk); in qmp_combo_runtime_suspend()
3368 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_combo_runtime_suspend()
3378 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); in qmp_combo_runtime_resume()
3380 if (!qmp->init_count) { in qmp_combo_runtime_resume()
3385 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); in qmp_combo_runtime_resume()
3389 ret = clk_prepare_enable(qmp->pipe_clk); in qmp_combo_runtime_resume()
3392 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); in qmp_combo_runtime_resume()
3408 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_vreg_init()
3409 struct device *dev = qmp->dev; in qmp_combo_vreg_init()
3410 int num = cfg->num_vregs; in qmp_combo_vreg_init()
3413 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_combo_vreg_init()
3414 if (!qmp->vregs) in qmp_combo_vreg_init()
3415 return -ENOMEM; in qmp_combo_vreg_init()
3418 qmp->vregs[i].supply = cfg->vreg_list[i].name; in qmp_combo_vreg_init()
3420 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_combo_vreg_init()
3427 ret = regulator_set_load(qmp->vregs[i].consumer, in qmp_combo_vreg_init()
3428 cfg->vreg_list[i].enable_load); in qmp_combo_vreg_init()
3431 qmp->vregs[i].supply); in qmp_combo_vreg_init()
3441 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_reset_init()
3442 struct device *dev = qmp->dev; in qmp_combo_reset_init()
3446 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_combo_reset_init()
3447 sizeof(*qmp->resets), GFP_KERNEL); in qmp_combo_reset_init()
3448 if (!qmp->resets) in qmp_combo_reset_init()
3449 return -ENOMEM; in qmp_combo_reset_init()
3451 for (i = 0; i < cfg->num_resets; i++) in qmp_combo_reset_init()
3452 qmp->resets[i].id = cfg->reset_list[i]; in qmp_combo_reset_init()
3454 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_combo_reset_init()
3463 struct device *dev = qmp->dev; in qmp_combo_clk_init()
3467 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_combo_clk_init()
3468 if (!qmp->clks) in qmp_combo_clk_init()
3469 return -ENOMEM; in qmp_combo_clk_init()
3472 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; in qmp_combo_clk_init()
3474 qmp->num_clks = num; in qmp_combo_clk_init()
3476 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_combo_clk_init()
3494 * +---------------+
3495 * | PHY block |<<---------------------------------------+
3497 * | +-------+ | +-----+ |
3498 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3499 * clk | +-------+ | +-----+
3500 * +---------------+
3504 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
3508 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); in phy_pipe_clk_register()
3513 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
3514 fixed->hw.init = &init; in phy_pipe_clk_register()
3516 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
3522 * +------------------------------+
3525 * | +-------------------+ |
3526 * | | (DP PLL/VCO) | |
3527 * | +---------+---------+ |
3529 * | +----------+-----------+ |
3531 * | +----------+-----------+ |
3532 * +------------------------------+
3534 * +---------<---------v------------>----------+
3536 * +--------v----------------+ |
3539 * +--------+----------------+ |
3548 * +--------<------------+-----------------+---<---+
3550 * +----v---------+ +--------v-----+ +--------v------+
3555 * +-------+------+ +-----+--------+ +--------+------+
3557 * v---->----------v-------------<------v
3559 * +----------+-----------------+
3561 * +---------+------------------+
3565 * for DP pixel clock
3570 switch (req->rate) { in qmp_dp_pixel_clk_determine_rate()
3576 return -EINVAL; in qmp_dp_pixel_clk_determine_rate()
3586 dp_opts = &qmp->dp_opts; in qmp_dp_pixel_clk_recalc_rate()
3588 switch (dp_opts->link_rate) { in qmp_dp_pixel_clk_recalc_rate()
3609 switch (req->rate) { in qmp_dp_link_clk_determine_rate()
3616 return -EINVAL; in qmp_dp_link_clk_determine_rate()
3626 dp_opts = &qmp->dp_opts; in qmp_dp_link_clk_recalc_rate()
3628 switch (dp_opts->link_rate) { in qmp_dp_link_clk_recalc_rate()
3633 return dp_opts->link_rate * 100000; in qmp_dp_link_clk_recalc_rate()
3647 unsigned int idx = clkspec->args[0]; in qmp_dp_clks_hw_get()
3651 return ERR_PTR(-EINVAL); in qmp_dp_clks_hw_get()
3655 return &qmp->dp_link_hw; in qmp_dp_clks_hw_get()
3657 return &qmp->dp_pixel_hw; in qmp_dp_clks_hw_get()
3666 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); in phy_dp_clks_register()
3669 qmp->dp_link_hw.init = &init; in phy_dp_clks_register()
3670 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); in phy_dp_clks_register()
3674 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); in phy_dp_clks_register()
3677 qmp->dp_pixel_hw.init = &init; in phy_dp_clks_register()
3678 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); in phy_dp_clks_register()
3689 switch (clkspec->args[0]) { in qmp_combo_clk_hw_get()
3691 return &qmp->pipe_clk_fixed.hw; in qmp_combo_clk_hw_get()
3693 return &qmp->dp_link_hw; in qmp_combo_clk_hw_get()
3695 return &qmp->dp_pixel_hw; in qmp_combo_clk_hw_get()
3698 return ERR_PTR(-EINVAL); in qmp_combo_clk_hw_get()
3717 if (usb_np == qmp->dev->of_node) in qmp_combo_register_clocks()
3718 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); in qmp_combo_register_clocks()
3724 &qmp->pipe_clk_fixed.hw); in qmp_combo_register_clocks()
3732 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); in qmp_combo_register_clocks()
3740 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); in qmp_combo_register_clocks()
3748 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_typec_switch_set()
3750 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) in qmp_combo_typec_switch_set()
3753 mutex_lock(&qmp->phy_mutex); in qmp_combo_typec_switch_set()
3754 qmp->orientation = orientation; in qmp_combo_typec_switch_set()
3756 if (qmp->init_count) { in qmp_combo_typec_switch_set()
3757 if (qmp->usb_init_count) in qmp_combo_typec_switch_set()
3758 qmp_combo_usb_power_off(qmp->usb_phy); in qmp_combo_typec_switch_set()
3762 if (qmp->usb_init_count) in qmp_combo_typec_switch_set()
3763 qmp_combo_usb_power_on(qmp->usb_phy); in qmp_combo_typec_switch_set()
3764 if (qmp->dp_init_count) in qmp_combo_typec_switch_set()
3765 cfg->dp_aux_init(qmp); in qmp_combo_typec_switch_set()
3767 mutex_unlock(&qmp->phy_mutex); in qmp_combo_typec_switch_set()
3776 typec_switch_unregister(qmp->sw); in qmp_combo_typec_unregister()
3782 struct device *dev = qmp->dev; in qmp_combo_typec_switch_register()
3785 sw_desc.fwnode = dev->fwnode; in qmp_combo_typec_switch_register()
3787 qmp->sw = typec_switch_register(dev, &sw_desc); in qmp_combo_typec_switch_register()
3788 if (IS_ERR(qmp->sw)) { in qmp_combo_typec_switch_register()
3789 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); in qmp_combo_typec_switch_register()
3790 return PTR_ERR(qmp->sw); in qmp_combo_typec_switch_register()
3804 struct device *dev = qmp->dev; in qmp_combo_parse_dt_legacy_dp()
3807 * Get memory resources from the DP child node: in qmp_combo_parse_dt_legacy_dp()
3808 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; in qmp_combo_parse_dt_legacy_dp()
3809 * tx2 -> 3; rx2 -> 4 in qmp_combo_parse_dt_legacy_dp()
3811 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP in qmp_combo_parse_dt_legacy_dp()
3814 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); in qmp_combo_parse_dt_legacy_dp()
3815 if (IS_ERR(qmp->dp_tx)) in qmp_combo_parse_dt_legacy_dp()
3816 return PTR_ERR(qmp->dp_tx); in qmp_combo_parse_dt_legacy_dp()
3818 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_parse_dt_legacy_dp()
3819 if (IS_ERR(qmp->dp_dp_phy)) in qmp_combo_parse_dt_legacy_dp()
3820 return PTR_ERR(qmp->dp_dp_phy); in qmp_combo_parse_dt_legacy_dp()
3822 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_parse_dt_legacy_dp()
3823 if (IS_ERR(qmp->dp_tx2)) in qmp_combo_parse_dt_legacy_dp()
3824 return PTR_ERR(qmp->dp_tx2); in qmp_combo_parse_dt_legacy_dp()
3831 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_parse_dt_legacy_usb()
3832 struct device *dev = qmp->dev; in qmp_combo_parse_dt_legacy_usb()
3836 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; in qmp_combo_parse_dt_legacy_usb()
3837 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 in qmp_combo_parse_dt_legacy_usb()
3839 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_combo_parse_dt_legacy_usb()
3840 if (IS_ERR(qmp->tx)) in qmp_combo_parse_dt_legacy_usb()
3841 return PTR_ERR(qmp->tx); in qmp_combo_parse_dt_legacy_usb()
3843 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_combo_parse_dt_legacy_usb()
3844 if (IS_ERR(qmp->rx)) in qmp_combo_parse_dt_legacy_usb()
3845 return PTR_ERR(qmp->rx); in qmp_combo_parse_dt_legacy_usb()
3847 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_combo_parse_dt_legacy_usb()
3848 if (IS_ERR(qmp->pcs)) in qmp_combo_parse_dt_legacy_usb()
3849 return PTR_ERR(qmp->pcs); in qmp_combo_parse_dt_legacy_usb()
3851 if (cfg->pcs_usb_offset) in qmp_combo_parse_dt_legacy_usb()
3852 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; in qmp_combo_parse_dt_legacy_usb()
3854 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_combo_parse_dt_legacy_usb()
3855 if (IS_ERR(qmp->tx2)) in qmp_combo_parse_dt_legacy_usb()
3856 return PTR_ERR(qmp->tx2); in qmp_combo_parse_dt_legacy_usb()
3858 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_combo_parse_dt_legacy_usb()
3859 if (IS_ERR(qmp->rx2)) in qmp_combo_parse_dt_legacy_usb()
3860 return PTR_ERR(qmp->rx2); in qmp_combo_parse_dt_legacy_usb()
3862 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_combo_parse_dt_legacy_usb()
3863 if (IS_ERR(qmp->pcs_misc)) { in qmp_combo_parse_dt_legacy_usb()
3864 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); in qmp_combo_parse_dt_legacy_usb()
3865 qmp->pcs_misc = NULL; in qmp_combo_parse_dt_legacy_usb()
3868 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); in qmp_combo_parse_dt_legacy_usb()
3869 if (IS_ERR(qmp->pipe_clk)) { in qmp_combo_parse_dt_legacy_usb()
3870 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), in qmp_combo_parse_dt_legacy_usb()
3880 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_combo_parse_dt_legacy()
3883 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_combo_parse_dt_legacy()
3884 if (IS_ERR(qmp->serdes)) in qmp_combo_parse_dt_legacy()
3885 return PTR_ERR(qmp->serdes); in qmp_combo_parse_dt_legacy()
3887 qmp->com = devm_platform_ioremap_resource(pdev, 1); in qmp_combo_parse_dt_legacy()
3888 if (IS_ERR(qmp->com)) in qmp_combo_parse_dt_legacy()
3889 return PTR_ERR(qmp->com); in qmp_combo_parse_dt_legacy()
3891 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); in qmp_combo_parse_dt_legacy()
3892 if (IS_ERR(qmp->dp_serdes)) in qmp_combo_parse_dt_legacy()
3893 return PTR_ERR(qmp->dp_serdes); in qmp_combo_parse_dt_legacy()
3903 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); in qmp_combo_parse_dt_legacy()
3907 qmp->num_clks = ret; in qmp_combo_parse_dt_legacy()
3914 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_combo_parse_dt()
3915 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_combo_parse_dt()
3916 const struct qmp_combo_offsets *offs = cfg->offsets; in qmp_combo_parse_dt()
3917 struct device *dev = qmp->dev; in qmp_combo_parse_dt()
3922 return -EINVAL; in qmp_combo_parse_dt()
3928 qmp->com = base + offs->com; in qmp_combo_parse_dt()
3929 qmp->tx = base + offs->txa; in qmp_combo_parse_dt()
3930 qmp->rx = base + offs->rxa; in qmp_combo_parse_dt()
3931 qmp->tx2 = base + offs->txb; in qmp_combo_parse_dt()
3932 qmp->rx2 = base + offs->rxb; in qmp_combo_parse_dt()
3934 qmp->serdes = base + offs->usb3_serdes; in qmp_combo_parse_dt()
3935 qmp->pcs_misc = base + offs->usb3_pcs_misc; in qmp_combo_parse_dt()
3936 qmp->pcs = base + offs->usb3_pcs; in qmp_combo_parse_dt()
3937 qmp->pcs_usb = base + offs->usb3_pcs_usb; in qmp_combo_parse_dt()
3939 qmp->dp_serdes = base + offs->dp_serdes; in qmp_combo_parse_dt()
3940 if (offs->dp_txa) { in qmp_combo_parse_dt()
3941 qmp->dp_tx = base + offs->dp_txa; in qmp_combo_parse_dt()
3942 qmp->dp_tx2 = base + offs->dp_txb; in qmp_combo_parse_dt()
3944 qmp->dp_tx = base + offs->txa; in qmp_combo_parse_dt()
3945 qmp->dp_tx2 = base + offs->txb; in qmp_combo_parse_dt()
3947 qmp->dp_dp_phy = base + offs->dp_dp_phy; in qmp_combo_parse_dt()
3953 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); in qmp_combo_parse_dt()
3954 if (IS_ERR(qmp->pipe_clk)) { in qmp_combo_parse_dt()
3955 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), in qmp_combo_parse_dt()
3966 if (args->args_count == 0) in qmp_combo_phy_xlate()
3967 return ERR_PTR(-EINVAL); in qmp_combo_phy_xlate()
3969 switch (args->args[0]) { in qmp_combo_phy_xlate()
3971 return qmp->usb_phy; in qmp_combo_phy_xlate()
3973 return qmp->dp_phy; in qmp_combo_phy_xlate()
3976 return ERR_PTR(-EINVAL); in qmp_combo_phy_xlate()
3982 struct device *dev = &pdev->dev; in qmp_combo_probe()
3989 return -ENOMEM; in qmp_combo_probe()
3991 qmp->dev = dev; in qmp_combo_probe()
3994 qmp->orientation = TYPEC_ORIENTATION_NORMAL; in qmp_combo_probe()
3996 qmp->cfg = of_device_get_match_data(dev); in qmp_combo_probe()
3997 if (!qmp->cfg) in qmp_combo_probe()
3998 return -EINVAL; in qmp_combo_probe()
4000 mutex_init(&qmp->phy_mutex); in qmp_combo_probe()
4011 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); in qmp_combo_probe()
4013 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); in qmp_combo_probe()
4016 return -EINVAL; in qmp_combo_probe()
4021 usb_np = of_node_get(dev->of_node); in qmp_combo_probe()
4022 dp_np = of_node_get(dev->of_node); in qmp_combo_probe()
4051 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); in qmp_combo_probe()
4052 if (IS_ERR(qmp->usb_phy)) { in qmp_combo_probe()
4053 ret = PTR_ERR(qmp->usb_phy); in qmp_combo_probe()
4058 phy_set_drvdata(qmp->usb_phy, qmp); in qmp_combo_probe()
4060 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
4061 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
4062 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
4063 dev_err(dev, "failed to create DP PHY: %d\n", ret); in qmp_combo_probe()
4067 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
4069 if (usb_np == dev->of_node) in qmp_combo_probe()
4087 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy",
4091 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
4095 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
4099 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
4103 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
4107 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
4111 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
4115 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
4119 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
4123 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
4127 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
4131 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
4135 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
4139 .compatible = "qcom,sm8750-qmp-usb3-dp-phy",
4143 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
4153 .name = "qcom-qmp-combo-phy",
4162 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");