Lines Matching full:edp
78 int (*com_power_on)(const struct qcom_edp *edp);
79 int (*com_resetsm_cntrl)(const struct qcom_edp *edp);
80 int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp);
81 int (*com_clk_fwd_cfg)(const struct qcom_edp *edp);
82 int (*com_configure_pll)(const struct qcom_edp *edp);
83 int (*com_configure_ssc)(const struct qcom_edp *edp);
84 int (*com_ldo_config)(const struct qcom_edp *edp);
102 void __iomem *edp; member
295 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_init() local
299 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
303 ret = clk_bulk_prepare_enable(edp->num_clks, edp->clks); in qcom_edp_phy_init()
307 memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg)); in qcom_edp_phy_init()
309 ret = edp->cfg->ver_ops->com_clk_fwd_cfg(edp); in qcom_edp_phy_init()
315 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
317 ret = edp->cfg->ver_ops->com_bias_en_clkbuflr(edp); in qcom_edp_phy_init()
321 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
327 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
329 if (!edp->is_edp) in qcom_edp_phy_init()
332 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
335 writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); in qcom_edp_phy_init()
339 PHY_AUX_REQ_ERR_MASK, edp->edp + DP_PHY_AUX_INTERRUPT_MASK); in qcom_edp_phy_init()
346 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
351 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts) in qcom_edp_set_voltages() argument
361 if (edp->is_edp) in qcom_edp_set_voltages()
362 cfg = edp->cfg->edp_swing_pre_emph_cfg; in qcom_edp_set_voltages()
364 cfg = edp->cfg->dp_swing_pre_emph_cfg; in qcom_edp_set_voltages()
382 ret = edp->cfg->ver_ops->com_ldo_config(edp); in qcom_edp_set_voltages()
386 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
387 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
389 writel(swing, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
390 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
398 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_configure() local
401 memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts)); in qcom_edp_phy_configure()
404 ret = qcom_edp_set_voltages(edp, dp_opts); in qcom_edp_phy_configure()
409 static int qcom_edp_configure_ssc(const struct qcom_edp *edp) in qcom_edp_configure_ssc() argument
411 return edp->cfg->ver_ops->com_configure_ssc(edp); in qcom_edp_configure_ssc()
414 static int qcom_edp_configure_pll(const struct qcom_edp *edp) in qcom_edp_configure_pll() argument
416 return edp->cfg->ver_ops->com_configure_pll(edp); in qcom_edp_configure_pll()
419 static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq) in qcom_edp_set_vco_div() argument
421 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_set_vco_div()
426 vco_div = edp->cfg->vco_div_cfg[0]; in qcom_edp_set_vco_div()
431 vco_div = edp->cfg->vco_div_cfg[1]; in qcom_edp_set_vco_div()
436 vco_div = edp->cfg->vco_div_cfg[2]; in qcom_edp_set_vco_div()
441 vco_div = edp->cfg->vco_div_cfg[3]; in qcom_edp_set_vco_div()
450 writel(vco_div, edp->edp + DP_PHY_VCO_DIV); in qcom_edp_set_vco_div()
455 static int qcom_edp_phy_power_on_v4(const struct qcom_edp *edp) in qcom_edp_phy_power_on_v4() argument
462 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v4()
463 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v4()
465 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, in qcom_edp_phy_power_on_v4()
469 static int qcom_edp_phy_com_resetsm_cntrl_v4(const struct qcom_edp *edp) in qcom_edp_phy_com_resetsm_cntrl_v4() argument
473 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v4()
475 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v4()
479 static int qcom_edp_com_clk_fwd_cfg_v4(const struct qcom_edp *edp) in qcom_edp_com_clk_fwd_cfg_v4() argument
484 static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp) in qcom_edp_com_bias_en_clkbuflr_v4() argument
487 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v4()
492 static int qcom_edp_com_configure_ssc_v4(const struct qcom_edp *edp) in qcom_edp_com_configure_ssc_v4() argument
494 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v4()
516 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v4()
517 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v4()
518 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v4()
519 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v4()
520 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v4()
521 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v4()
526 static int qcom_edp_com_configure_pll_v4(const struct qcom_edp *edp) in qcom_edp_com_configure_pll_v4() argument
528 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v4()
578 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v4()
579 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v4()
580 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v4()
581 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v4()
582 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v4()
583 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v4()
584 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); in qcom_edp_com_configure_pll_v4()
585 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v4()
586 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v4()
587 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v4()
588 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v4()
589 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v4()
590 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v4()
591 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v4()
592 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v4()
593 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v4()
594 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); in qcom_edp_com_configure_pll_v4()
595 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v4()
596 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v4()
597 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v4()
598 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v4()
599 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v4()
601 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); in qcom_edp_com_configure_pll_v4()
602 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); in qcom_edp_com_configure_pll_v4()
603 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v4()
604 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_configure_pll_v4()
605 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v4()
606 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v4()
607 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v4()
612 static int qcom_edp_ldo_config_v3(const struct qcom_edp *edp) in qcom_edp_ldo_config_v3() argument
614 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_ldo_config_v3()
617 if (!edp->is_edp) in qcom_edp_ldo_config_v3()
624 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_ldo_config_v3()
625 writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_ldo_config_v3()
630 static int qcom_edp_ldo_config_v4(const struct qcom_edp *edp) in qcom_edp_ldo_config_v4() argument
632 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_ldo_config_v4()
635 if (!edp->is_edp) in qcom_edp_ldo_config_v4()
642 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_ldo_config_v4()
643 writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_ldo_config_v4()
710 static int qcom_edp_phy_power_on_v6(const struct qcom_edp *edp) in qcom_edp_phy_power_on_v6() argument
717 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v6()
718 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v6()
720 return readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS, in qcom_edp_phy_power_on_v6()
724 static int qcom_edp_phy_com_resetsm_cntrl_v6(const struct qcom_edp *edp) in qcom_edp_phy_com_resetsm_cntrl_v6() argument
728 writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v6()
730 return readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v6()
734 static int qcom_edp_com_bias_en_clkbuflr_v6(const struct qcom_edp *edp) in qcom_edp_com_bias_en_clkbuflr_v6() argument
737 writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v6()
742 static int qcom_edp_com_configure_ssc_v6(const struct qcom_edp *edp) in qcom_edp_com_configure_ssc_v6() argument
744 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v6()
766 writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v6()
767 writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v6()
768 writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v6()
769 writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v6()
770 writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v6()
771 writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v6()
776 static int qcom_edp_com_configure_pll_v6(const struct qcom_edp *edp) in qcom_edp_com_configure_pll_v6() argument
778 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v6()
838 writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v6()
839 writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v6()
840 writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v6()
841 writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v6()
842 writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v6()
843 writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v6()
844 writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1); in qcom_edp_com_configure_pll_v6()
845 writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v6()
846 writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v6()
847 writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v6()
848 writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v6()
849 writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v6()
850 writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v6()
851 writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v6()
852 writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v6()
853 writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v6()
854 writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1); in qcom_edp_com_configure_pll_v6()
855 writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v6()
856 writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v6()
857 writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v6()
858 writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v6()
859 writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v6()
861 writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER); in qcom_edp_com_configure_pll_v6()
862 writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0); in qcom_edp_com_configure_pll_v6()
863 writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v6()
864 writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); in qcom_edp_com_configure_pll_v6()
865 writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v6()
866 writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v6()
867 writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v6()
869 writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0); in qcom_edp_com_configure_pll_v6()
870 writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0); in qcom_edp_com_configure_pll_v6()
875 static int qcom_edp_ldo_config_v6(const struct qcom_edp *edp) in qcom_edp_ldo_config_v6() argument
877 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_ldo_config_v6()
880 if (!edp->is_edp) in qcom_edp_ldo_config_v6()
887 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_ldo_config_v6()
888 writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_ldo_config_v6()
911 static int qcom_edp_com_configure_ssc_v8(const struct qcom_edp *edp) in qcom_edp_com_configure_ssc_v8() argument
913 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_ssc_v8()
935 writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER); in qcom_edp_com_configure_ssc_v8()
936 writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1); in qcom_edp_com_configure_ssc_v8()
937 writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1); in qcom_edp_com_configure_ssc_v8()
938 writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2); in qcom_edp_com_configure_ssc_v8()
939 writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0); in qcom_edp_com_configure_ssc_v8()
940 writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0); in qcom_edp_com_configure_ssc_v8()
945 static int qcom_edp_com_configure_pll_v8(const struct qcom_edp *edp) in qcom_edp_com_configure_pll_v8() argument
947 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_com_configure_pll_v8()
997 writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL); in qcom_edp_com_configure_pll_v8()
998 writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL); in qcom_edp_com_configure_pll_v8()
999 writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL); in qcom_edp_com_configure_pll_v8()
1000 writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1); in qcom_edp_com_configure_pll_v8()
1001 writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE); in qcom_edp_com_configure_pll_v8()
1002 writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT); in qcom_edp_com_configure_pll_v8()
1003 writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1); in qcom_edp_com_configure_pll_v8()
1004 writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO); in qcom_edp_com_configure_pll_v8()
1005 writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN); in qcom_edp_com_configure_pll_v8()
1006 writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0); in qcom_edp_com_configure_pll_v8()
1007 writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0); in qcom_edp_com_configure_pll_v8()
1008 writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0); in qcom_edp_com_configure_pll_v8()
1009 writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0); in qcom_edp_com_configure_pll_v8()
1010 writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0); in qcom_edp_com_configure_pll_v8()
1011 writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0); in qcom_edp_com_configure_pll_v8()
1012 writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0); in qcom_edp_com_configure_pll_v8()
1013 writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1); in qcom_edp_com_configure_pll_v8()
1014 writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0); in qcom_edp_com_configure_pll_v8()
1015 writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0); in qcom_edp_com_configure_pll_v8()
1016 writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP); in qcom_edp_com_configure_pll_v8()
1017 writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0); in qcom_edp_com_configure_pll_v8()
1018 writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0); in qcom_edp_com_configure_pll_v8()
1020 writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER); in qcom_edp_com_configure_pll_v8()
1021 writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0); in qcom_edp_com_configure_pll_v8()
1022 writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL); in qcom_edp_com_configure_pll_v8()
1023 writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_configure_pll_v8()
1024 writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN); in qcom_edp_com_configure_pll_v8()
1025 writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0); in qcom_edp_com_configure_pll_v8()
1026 writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0); in qcom_edp_com_configure_pll_v8()
1028 writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0); in qcom_edp_com_configure_pll_v8()
1029 writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0); in qcom_edp_com_configure_pll_v8()
1035 static int qcom_edp_phy_com_resetsm_cntrl_v8(const struct qcom_edp *edp) in qcom_edp_phy_com_resetsm_cntrl_v8() argument
1039 writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL); in qcom_edp_phy_com_resetsm_cntrl_v8()
1041 return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_C_READY_STATUS, in qcom_edp_phy_com_resetsm_cntrl_v8()
1045 static int qcom_edp_com_clk_fwd_cfg_v8(const struct qcom_edp *edp) in qcom_edp_com_clk_fwd_cfg_v8() argument
1047 writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1); in qcom_edp_com_clk_fwd_cfg_v8()
1052 static int qcom_edp_com_bias_en_clkbuflr_v8(const struct qcom_edp *edp) in qcom_edp_com_bias_en_clkbuflr_v8() argument
1055 writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_com_bias_en_clkbuflr_v8()
1060 static int qcom_edp_phy_power_on_v8(const struct qcom_edp *edp) in qcom_edp_phy_power_on_v8() argument
1067 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_on_v8()
1068 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_power_on_v8()
1070 return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_CMN_STATUS, in qcom_edp_phy_power_on_v8()
1094 const struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_power_on() local
1101 ret = edp->cfg->ver_ops->com_power_on(edp); in qcom_edp_phy_power_on()
1105 ret = edp->cfg->ver_ops->com_ldo_config(edp); in qcom_edp_phy_power_on()
1109 writel(0x00, edp->tx0 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
1110 writel(0x00, edp->tx1 + TXn_LANE_MODE_1); in qcom_edp_phy_power_on()
1112 if (edp->dp_opts.ssc) { in qcom_edp_phy_power_on()
1113 ret = qcom_edp_configure_ssc(edp); in qcom_edp_phy_power_on()
1118 ret = qcom_edp_configure_pll(edp); in qcom_edp_phy_power_on()
1123 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL); in qcom_edp_phy_power_on()
1124 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL); in qcom_edp_phy_power_on()
1127 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
1128 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
1129 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
1130 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
1131 writel(0x04, edp->tx0 + TXn_TX_BAND); in qcom_edp_phy_power_on()
1134 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
1135 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE); in qcom_edp_phy_power_on()
1136 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN); in qcom_edp_phy_power_on()
1137 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); in qcom_edp_phy_power_on()
1138 writel(0x04, edp->tx1 + TXn_TX_BAND); in qcom_edp_phy_power_on()
1140 ret = qcom_edp_set_vco_div(edp, &pixel_freq); in qcom_edp_phy_power_on()
1144 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1145 writel(0x05, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1146 writel(0x01, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1147 writel(0x09, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1149 ret = edp->cfg->ver_ops->com_resetsm_cntrl(edp); in qcom_edp_phy_power_on()
1153 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1154 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
1155 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
1156 writel(0x00, edp->tx0 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
1157 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
1158 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
1159 writel(0x00, edp->tx1 + TXn_TX_POL_INV); in qcom_edp_phy_power_on()
1160 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
1161 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET); in qcom_edp_phy_power_on()
1162 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
1163 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
1164 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); in qcom_edp_phy_power_on()
1165 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); in qcom_edp_phy_power_on()
1167 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
1168 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL); in qcom_edp_phy_power_on()
1169 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
1170 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); in qcom_edp_phy_power_on()
1172 if (edp->dp_opts.lanes == 1) { in qcom_edp_phy_power_on()
1178 } else if (edp->dp_opts.lanes == 2) { in qcom_edp_phy_power_on()
1192 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
1193 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
1194 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); in qcom_edp_phy_power_on()
1195 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); in qcom_edp_phy_power_on()
1196 writel(cfg1, edp->edp + DP_PHY_CFG_1); in qcom_edp_phy_power_on()
1198 writel(0x18, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1201 writel(0x19, edp->edp + DP_PHY_CFG); in qcom_edp_phy_power_on()
1203 ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS, in qcom_edp_phy_power_on()
1208 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); in qcom_edp_phy_power_on()
1209 clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); in qcom_edp_phy_power_on()
1216 const struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_power_off() local
1218 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_power_off()
1225 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_set_mode() local
1230 edp->is_edp = submode == PHY_SUBMODE_EDP; in qcom_edp_phy_set_mode()
1237 struct qcom_edp *edp = phy_get_drvdata(phy); in qcom_edp_phy_exit() local
1239 clk_bulk_disable_unprepare(edp->num_clks, edp->clks); in qcom_edp_phy_exit()
1240 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_exit()
1262 * | | (EDP PLL/VCO) | |
1301 * for EDP pixel clock
1321 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_pixel_hw); in qcom_edp_dp_pixel_clk_recalc_rate() local
1322 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_pixel_clk_recalc_rate()
1361 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_link_hw); in qcom_edp_dp_link_clk_recalc_rate() local
1362 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; in qcom_edp_dp_link_clk_recalc_rate()
1381 static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) in qcom_edp_clks_register() argument
1388 data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); in qcom_edp_clks_register()
1393 snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
1396 edp->dp_link_hw.init = &init; in qcom_edp_clks_register()
1397 ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw); in qcom_edp_clks_register()
1401 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev)); in qcom_edp_clks_register()
1404 edp->dp_pixel_hw.init = &init; in qcom_edp_clks_register()
1405 ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw); in qcom_edp_clks_register()
1409 data->hws[0] = &edp->dp_link_hw; in qcom_edp_clks_register()
1410 data->hws[1] = &edp->dp_pixel_hw; in qcom_edp_clks_register()
1412 return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); in qcom_edp_clks_register()
1419 struct qcom_edp *edp; in qcom_edp_phy_probe() local
1422 edp = devm_kzalloc(dev, sizeof(*edp), GFP_KERNEL); in qcom_edp_phy_probe()
1423 if (!edp) in qcom_edp_phy_probe()
1426 edp->dev = dev; in qcom_edp_phy_probe()
1427 edp->cfg = of_device_get_match_data(&pdev->dev); in qcom_edp_phy_probe()
1428 edp->is_edp = edp->cfg->is_edp; in qcom_edp_phy_probe()
1430 edp->edp = devm_platform_ioremap_resource(pdev, 0); in qcom_edp_phy_probe()
1431 if (IS_ERR(edp->edp)) in qcom_edp_phy_probe()
1432 return PTR_ERR(edp->edp); in qcom_edp_phy_probe()
1434 edp->tx0 = devm_platform_ioremap_resource(pdev, 1); in qcom_edp_phy_probe()
1435 if (IS_ERR(edp->tx0)) in qcom_edp_phy_probe()
1436 return PTR_ERR(edp->tx0); in qcom_edp_phy_probe()
1438 edp->tx1 = devm_platform_ioremap_resource(pdev, 2); in qcom_edp_phy_probe()
1439 if (IS_ERR(edp->tx1)) in qcom_edp_phy_probe()
1440 return PTR_ERR(edp->tx1); in qcom_edp_phy_probe()
1442 edp->pll = devm_platform_ioremap_resource(pdev, 3); in qcom_edp_phy_probe()
1443 if (IS_ERR(edp->pll)) in qcom_edp_phy_probe()
1444 return PTR_ERR(edp->pll); in qcom_edp_phy_probe()
1446 edp->num_clks = devm_clk_bulk_get_all(dev, &edp->clks); in qcom_edp_phy_probe()
1447 if (edp->num_clks < 0) in qcom_edp_phy_probe()
1448 return dev_err_probe(dev, edp->num_clks, "failed to get clocks\n"); in qcom_edp_phy_probe()
1450 edp->supplies[0].supply = "vdda-phy"; in qcom_edp_phy_probe()
1451 edp->supplies[1].supply = "vdda-pll"; in qcom_edp_phy_probe()
1452 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_probe()
1456 ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ in qcom_edp_phy_probe()
1458 dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); in qcom_edp_phy_probe()
1462 ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ in qcom_edp_phy_probe()
1464 dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); in qcom_edp_phy_probe()
1468 ret = qcom_edp_clks_register(edp, pdev->dev.of_node); in qcom_edp_phy_probe()
1472 edp->phy = devm_phy_create(dev, pdev->dev.of_node, &qcom_edp_ops); in qcom_edp_phy_probe()
1473 if (IS_ERR(edp->phy)) { in qcom_edp_phy_probe()
1475 return PTR_ERR(edp->phy); in qcom_edp_phy_probe()
1478 phy_set_drvdata(edp->phy, edp); in qcom_edp_phy_probe()
1486 { .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
1487 { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
1488 { .compatible = "qcom,sc8180x-edp-phy", .data = &sc8180x_dp_phy_cfg, },
1490 { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
1499 .name = "qcom-edp-phy",
1507 MODULE_DESCRIPTION("Qualcomm eDP QMP PHY driver");