Lines Matching +full:serdes +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
18 #include <linux/clk.h>
104 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
106 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
107 bool no_pwrcycle:1; /* Omit initial power-cycle */
236 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
246 bool no_pwrcycle:1; /* Omit initial power-cycle */
652 switch (macro->serdesmode) { in sparx5_sd10g25_get_mode_preset()
654 if (macro->speed == SPEED_25000) in sparx5_sd10g25_get_mode_preset()
656 else if (macro->speed == SPEED_10000) in sparx5_sd10g25_get_mode_preset()
658 else if (macro->speed == SPEED_5000) in sparx5_sd10g25_get_mode_preset()
669 return -EINVAL; in sparx5_sd10g25_get_mode_preset()
681 switch (macro->serdesmode) { in sparx5_sd10g28_get_mode_preset()
683 if (macro->speed == SPEED_10000) { in sparx5_sd10g28_get_mode_preset()
685 } else if (macro->speed == SPEED_5000) { in sparx5_sd10g28_get_mode_preset()
686 if (args->is_6g) in sparx5_sd10g28_get_mode_preset()
691 dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)", in sparx5_sd10g28_get_mode_preset()
692 __func__, macro->speed, macro->sidx, in sparx5_sd10g28_get_mode_preset()
693 macro->serdesmode); in sparx5_sd10g28_get_mode_preset()
694 return -EINVAL; in sparx5_sd10g28_get_mode_preset()
720 u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth); in sparx5_sd25g28_get_params()
723 .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, in sparx5_sd25g28_get_params()
724 .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, in sparx5_sd25g28_get_params()
725 .cfg_vco_div_mode_1_0 = mode->vco_div_mode, in sparx5_sd25g28_get_params()
726 .cfg_pre_divsel_1_0 = mode->pre_divsel, in sparx5_sd25g28_get_params()
727 .cfg_sel_div_3_0 = mode->sel_div, in sparx5_sd25g28_get_params()
729 .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth, in sparx5_sd25g28_get_params()
730 .cfg_tx_prediv_1_0 = mode->tx_pre_div, in sparx5_sd25g28_get_params()
731 .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth, in sparx5_sd25g28_get_params()
732 .cfg_tx_subrate_2_0 = mode->subrate, in sparx5_sd25g28_get_params()
733 .cfg_rx_subrate_2_0 = mode->subrate, in sparx5_sd25g28_get_params()
736 .cfg_dfeck_en = mode->dfe_enable, in sparx5_sd25g28_get_params()
737 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
739 .cfg_dfetap_en_5_1 = mode->dfe_tap, in sparx5_sd25g28_get_params()
742 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, in sparx5_sd25g28_get_params()
743 .cfg_pi_DFE_en = mode->dfe_enable, in sparx5_sd25g28_get_params()
756 .cfg_itx_ipdriver_base_2_0 = mode->txmargin, in sparx5_sd25g28_get_params()
757 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, in sparx5_sd25g28_get_params()
758 .cfg_tap_main = media->cfg_tap_main, in sparx5_sd25g28_get_params()
759 .cfg_en_main = media->cfg_en_main, in sparx5_sd25g28_get_params()
760 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, in sparx5_sd25g28_get_params()
761 .cfg_en_adv = media->cfg_en_adv, in sparx5_sd25g28_get_params()
762 .cfg_en_dly = media->cfg_en_dly, in sparx5_sd25g28_get_params()
767 .cfg_pll_reserve_3_0 = args->com_pll_reserve, in sparx5_sd25g28_get_params()
768 .l0_cfg_txcal_en = mode->com_txcal_en, in sparx5_sd25g28_get_params()
769 .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb, in sparx5_sd25g28_get_params()
770 .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb, in sparx5_sd25g28_get_params()
771 .cfg_tx_reserve_15_8 = mode->tx_reserve_msb, in sparx5_sd25g28_get_params()
772 .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb, in sparx5_sd25g28_get_params()
773 .cfg_bw_1_0 = mode->bw, in sparx5_sd25g28_get_params()
782 .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0, in sparx5_sd25g28_get_params()
785 .cfg_ctle_rstn = mode->cfg_ctle_rstn, in sparx5_sd25g28_get_params()
786 .r_dfe_rstn = mode->r_dfe_rstn, in sparx5_sd25g28_get_params()
787 .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0, in sparx5_sd25g28_get_params()
788 .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base, in sparx5_sd25g28_get_params()
791 .cfg_rxterm_2_0 = mode->rxterm, in sparx5_sd25g28_get_params()
795 .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0, in sparx5_sd25g28_get_params()
799 .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0, in sparx5_sd25g28_get_params()
800 .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0, in sparx5_sd25g28_get_params()
806 .cfg_en_dfedig = mode->dfe_enable, in sparx5_sd25g28_get_params()
809 .reg_rst = args->reg_rst, in sparx5_sd25g28_get_params()
817 .r_tx_pol_inv = args->txinvert, in sparx5_sd25g28_get_params()
818 .r_rx_pol_inv = args->rxinvert, in sparx5_sd25g28_get_params()
830 u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth); in sparx5_sd10g28_get_params()
832 .skip_cmu_cfg = args->skip_cmu_cfg, in sparx5_sd10g28_get_params()
833 .is_6g = args->is_6g, in sparx5_sd10g28_get_params()
834 .cmu_sel = mode->cmu_sel, in sparx5_sd10g28_get_params()
835 .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6, in sparx5_sd10g28_get_params()
836 .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2), in sparx5_sd10g28_get_params()
837 .cfg_lane_reserve_15_8 = mode->duty_cycle, in sparx5_sd10g28_get_params()
838 .cfg_txrate_1_0 = mode->rate, in sparx5_sd10g28_get_params()
839 .cfg_rxrate_1_0 = mode->rate, in sparx5_sd10g28_get_params()
840 .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX, in sparx5_sd10g28_get_params()
847 .cfg_dfeck_en = mode->dfe_enable, in sparx5_sd10g28_get_params()
848 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
849 .cfg_dfetap_en_5_1 = mode->dfe_tap, in sparx5_sd10g28_get_params()
850 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, in sparx5_sd10g28_get_params()
851 .cfg_pi_DFE_en = mode->dfe_enable, in sparx5_sd10g28_get_params()
861 .cfg_pd_sq = mode->dfe_enable, in sparx5_sd10g28_get_params()
865 .cfg_en_adv = media->cfg_en_adv, in sparx5_sd10g28_get_params()
867 .cfg_en_dly = media->cfg_en_dly, in sparx5_sd10g28_get_params()
868 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, in sparx5_sd10g28_get_params()
869 .cfg_tap_main = media->cfg_tap_main, in sparx5_sd10g28_get_params()
870 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, in sparx5_sd10g28_get_params()
871 .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0, in sparx5_sd10g28_get_params()
872 .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0, in sparx5_sd10g28_get_params()
873 .cfg_eq_res_3_0 = media->cfg_eq_res_3_0, in sparx5_sd10g28_get_params()
874 .cfg_eq_r_byp = media->cfg_eq_r_byp, in sparx5_sd10g28_get_params()
875 .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0, in sparx5_sd10g28_get_params()
876 .cfg_en_dfedig = mode->dfe_enable, in sparx5_sd10g28_get_params()
880 .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6), in sparx5_sd10g28_get_params()
881 .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63), in sparx5_sd10g28_get_params()
882 .cfg_txswing_half = (args->txmargin), in sparx5_sd10g28_get_params()
894 .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
895 .cfg_pi_bw_gen2 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
896 .cfg_pi_bw_gen3 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
897 .cfg_pi_bw_gen4 = mode->pi_bw_gen1, in sparx5_sd10g28_get_params()
901 .cfg_rstn_dfedig = mode->dfe_enable, in sparx5_sd10g28_get_params()
902 .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0, in sparx5_sd10g28_get_params()
923 .r_tx_pol_inv = args->txinvert, in sparx5_sd10g28_get_params()
924 .r_rx_pol_inv = args->rxinvert, in sparx5_sd10g28_get_params()
936 void __iomem **regs = priv->regs; in sparx5_cmu_apply_cfg()
937 struct device *dev = priv->dev; in sparx5_cmu_apply_cfg()
1040 return -EINVAL; in sparx5_cmu_apply_cfg()
1065 /* Map of 6G/10G serdes mode and index to CMU index. */
1090 /* Get the index of the CMU which provides the clock for the specified serdes
1150 if (params->reg_rst == 1) { in sparx5_sd25g28_reset()
1166 struct sparx5_serdes_private *priv = macro->priv; in sparx5_sd25g28_apply_params()
1167 void __iomem **regs = priv->regs; in sparx5_sd25g28_apply_params()
1168 struct device *dev = priv->dev; in sparx5_sd25g28_apply_params()
1169 u32 sd_index = macro->stpidx; in sparx5_sd25g28_apply_params()
1183 (params->r_d_width_ctrl_from_hwt) | in sparx5_sd25g28_apply_params()
1184 SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual), in sparx5_sd25g28_apply_params()
1191 (params->cfg_common_reserve_7_0), in sparx5_sd25g28_apply_params()
1196 sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy), in sparx5_sd25g28_apply_params()
1202 (params->cfg_pll_reserve_3_0), in sparx5_sd25g28_apply_params()
1207 sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en), in sparx5_sd25g28_apply_params()
1213 (params->l0_cfg_tx_reserve_15_8), in sparx5_sd25g28_apply_params()
1219 (params->l0_cfg_tx_reserve_7_0), in sparx5_sd25g28_apply_params()
1254 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0), in sparx5_sd25g28_apply_params()
1260 (params->r_txfifo_ck_div_pmad_2_0) | in sparx5_sd25g28_apply_params()
1262 (params->r_rxfifo_ck_div_pmad_2_0), in sparx5_sd25g28_apply_params()
1268 sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) | in sparx5_sd25g28_apply_params()
1270 (params->cfg_vco_div_mode_1_0), in sparx5_sd25g28_apply_params()
1277 (params->cfg_pre_divsel_1_0), in sparx5_sd25g28_apply_params()
1282 sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0), in sparx5_sd25g28_apply_params()
1293 (params->cfg_pma_tx_ck_bitwidth_2_0), in sparx5_sd25g28_apply_params()
1299 (params->cfg_tx_prediv_1_0), in sparx5_sd25g28_apply_params()
1305 (params->cfg_rxdiv_sel_2_0), in sparx5_sd25g28_apply_params()
1311 (params->cfg_tx_subrate_2_0), in sparx5_sd25g28_apply_params()
1317 (params->cfg_rx_subrate_2_0), in sparx5_sd25g28_apply_params()
1322 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd25g28_apply_params()
1328 (params->cfg_dfetap_en_5_1), in sparx5_sd25g28_apply_params()
1333 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1338 sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en), in sparx5_sd25g28_apply_params()
1343 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd), in sparx5_sd25g28_apply_params()
1349 (params->cfg_itx_ipdriver_base_2_0), in sparx5_sd25g28_apply_params()
1354 sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0), in sparx5_sd25g28_apply_params()
1359 sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0), in sparx5_sd25g28_apply_params()
1364 sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd25g28_apply_params()
1365 SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly), in sparx5_sd25g28_apply_params()
1372 (params->cfg_tx_reserve_15_8), in sparx5_sd25g28_apply_params()
1378 (params->cfg_tx_reserve_7_0), in sparx5_sd25g28_apply_params()
1383 sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0), in sparx5_sd25g28_apply_params()
1389 (params->cfg_txcal_man_en), in sparx5_sd25g28_apply_params()
1395 (params->cfg_txcal_shift_code_5_0), in sparx5_sd25g28_apply_params()
1401 (params->cfg_txcal_valid_sel_3_0), in sparx5_sd25g28_apply_params()
1406 sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0), in sparx5_sd25g28_apply_params()
1411 sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0), in sparx5_sd25g28_apply_params()
1416 sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0), in sparx5_sd25g28_apply_params()
1422 (params->cfg_dis_2ndorder), in sparx5_sd25g28_apply_params()
1427 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn), in sparx5_sd25g28_apply_params()
1433 (params->cfg_itx_ipcml_base_1_0), in sparx5_sd25g28_apply_params()
1439 (params->cfg_rx_reserve_7_0), in sparx5_sd25g28_apply_params()
1445 (params->cfg_rx_reserve_15_8), in sparx5_sd25g28_apply_params()
1450 sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) | in sparx5_sd25g28_apply_params()
1451 SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0), in sparx5_sd25g28_apply_params()
1458 (params->cfg_vga_ctrl_byp_4_0), in sparx5_sd25g28_apply_params()
1464 (params->cfg_eqr_force_3_0), in sparx5_sd25g28_apply_params()
1470 (params->cfg_eqc_force_3_0) | in sparx5_sd25g28_apply_params()
1471 SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd), in sparx5_sd25g28_apply_params()
1478 (params->cfg_sum_setcm_en), in sparx5_sd25g28_apply_params()
1484 (params->cfg_init_pos_iscan_6_0), in sparx5_sd25g28_apply_params()
1490 (params->cfg_init_pos_ipi_6_0), in sparx5_sd25g28_apply_params()
1495 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), in sparx5_sd25g28_apply_params()
1501 (params->cfg_dfedig_m_2_0), in sparx5_sd25g28_apply_params()
1506 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig), in sparx5_sd25g28_apply_params()
1511 sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) | in sparx5_sd25g28_apply_params()
1512 SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv), in sparx5_sd25g28_apply_params()
1518 sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) | in sparx5_sd25g28_apply_params()
1519 SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en), in sparx5_sd25g28_apply_params()
1525 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en), in sparx5_sd25g28_apply_params()
1530 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd25g28_apply_params()
1574 return -EINVAL; in sparx5_sd25g28_apply_params()
1582 return -EINVAL; in sparx5_sd25g28_apply_params()
1605 (params->cfg_alos_thr_2_0), in sparx5_sd25g28_apply_params()
1625 /* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */ in sparx5_sd10g28_reset()
1640 struct sparx5_serdes_private *priv = macro->priv; in sparx5_sd10g28_apply_params()
1641 void __iomem **regs = priv->regs; in sparx5_sd10g28_apply_params()
1642 struct device *dev = priv->dev; in sparx5_sd10g28_apply_params()
1643 u32 lane_index = macro->sidx; in sparx5_sd10g28_apply_params()
1644 u32 sd_index = macro->stpidx; in sparx5_sd10g28_apply_params()
1649 /* Do not configure serdes if CMU is not to be configured too */ in sparx5_sd10g28_apply_params()
1650 if (params->skip_cmu_cfg) in sparx5_sd10g28_apply_params()
1653 cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index); in sparx5_sd10g28_apply_params()
1658 if (params->is_6g) in sparx5_sd10g28_apply_params()
1706 sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) | in sparx5_sd10g28_apply_params()
1707 SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel), in sparx5_sd10g28_apply_params()
1714 (params->cfg_lane_reserve_7_0), in sparx5_sd10g28_apply_params()
1720 (params->cfg_ssc_rtl_clk_sel), in sparx5_sd10g28_apply_params()
1726 (params->cfg_txrate_1_0) | in sparx5_sd10g28_apply_params()
1728 (params->cfg_rxrate_1_0), in sparx5_sd10g28_apply_params()
1735 (params->r_d_width_ctrl_2_0), in sparx5_sd10g28_apply_params()
1741 (params->cfg_pma_tx_ck_bitwidth_2_0), in sparx5_sd10g28_apply_params()
1747 (params->cfg_rxdiv_sel_2_0), in sparx5_sd10g28_apply_params()
1753 (params->r_pcs2pma_phymode_4_0), in sparx5_sd10g28_apply_params()
1758 sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), in sparx5_sd10g28_apply_params()
1764 (params->cfg_dfeck_en) | in sparx5_sd10g28_apply_params()
1765 SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) | in sparx5_sd10g28_apply_params()
1767 (params->cfg_erramp_pd), in sparx5_sd10g28_apply_params()
1775 (params->cfg_dfetap_en_5_1), in sparx5_sd10g28_apply_params()
1781 (params->cfg_pi_DFE_en), in sparx5_sd10g28_apply_params()
1786 sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) | in sparx5_sd10g28_apply_params()
1787 SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) | in sparx5_sd10g28_apply_params()
1788 SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) | in sparx5_sd10g28_apply_params()
1790 (params->cfg_tap_adv_3_0), in sparx5_sd10g28_apply_params()
1798 sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main), in sparx5_sd10g28_apply_params()
1804 (params->cfg_tap_dly_4_0), in sparx5_sd10g28_apply_params()
1810 (params->cfg_vga_ctrl_3_0), in sparx5_sd10g28_apply_params()
1816 (params->cfg_vga_cp_2_0), in sparx5_sd10g28_apply_params()
1822 (params->cfg_eq_res_3_0), in sparx5_sd10g28_apply_params()
1827 sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp), in sparx5_sd10g28_apply_params()
1833 (params->cfg_eq_c_force_3_0) | in sparx5_sd10g28_apply_params()
1835 (params->cfg_sum_setcm_en), in sparx5_sd10g28_apply_params()
1842 (params->cfg_en_dfedig), in sparx5_sd10g28_apply_params()
1848 (params->cfg_en_preemph), in sparx5_sd10g28_apply_params()
1854 (params->cfg_itx_ippreemp_base_1_0) | in sparx5_sd10g28_apply_params()
1856 (params->cfg_itx_ipdriver_base_2_0), in sparx5_sd10g28_apply_params()
1863 (params->cfg_ibias_tune_reserve_5_0), in sparx5_sd10g28_apply_params()
1869 (params->cfg_txswing_half), in sparx5_sd10g28_apply_params()
1875 (params->cfg_dis_2nd_order), in sparx5_sd10g28_apply_params()
1881 (params->cfg_rx_ssc_lh), in sparx5_sd10g28_apply_params()
1887 (params->cfg_pi_floop_steps_1_0), in sparx5_sd10g28_apply_params()
1893 (params->cfg_pi_ext_dac_23_16), in sparx5_sd10g28_apply_params()
1899 (params->cfg_pi_ext_dac_15_8), in sparx5_sd10g28_apply_params()
1905 (params->cfg_iscan_ext_dac_7_0), in sparx5_sd10g28_apply_params()
1911 (params->cfg_cdr_kf_gen1_2_0), in sparx5_sd10g28_apply_params()
1917 (params->r_cdr_m_gen1_7_0), in sparx5_sd10g28_apply_params()
1923 (params->cfg_pi_bw_gen1_3_0), in sparx5_sd10g28_apply_params()
1929 (params->cfg_pi_ext_dac_7_0), in sparx5_sd10g28_apply_params()
1934 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps), in sparx5_sd10g28_apply_params()
1940 (params->cfg_mp_max_3_0), in sparx5_sd10g28_apply_params()
1946 (params->cfg_rstn_dfedig), in sparx5_sd10g28_apply_params()
1952 (params->cfg_alos_thr_3_0), in sparx5_sd10g28_apply_params()
1958 (params->cfg_predrv_slewrate_1_0), in sparx5_sd10g28_apply_params()
1964 (params->cfg_itx_ipcml_base_1_0), in sparx5_sd10g28_apply_params()
1970 (params->cfg_ip_pre_base_1_0), in sparx5_sd10g28_apply_params()
1976 (params->cfg_lane_reserve_15_8), in sparx5_sd10g28_apply_params()
1982 (params->r_en_auto_cdr_rstn), in sparx5_sd10g28_apply_params()
1988 (params->cfg_oscal_afe) | in sparx5_sd10g28_apply_params()
1990 (params->cfg_pd_osdac_afe), in sparx5_sd10g28_apply_params()
1997 (params->cfg_resetb_oscal_afe[0]), in sparx5_sd10g28_apply_params()
2003 (params->cfg_resetb_oscal_afe[1]), in sparx5_sd10g28_apply_params()
2009 (params->r_tx_pol_inv) | in sparx5_sd10g28_apply_params()
2011 (params->r_rx_pol_inv), in sparx5_sd10g28_apply_params()
2018 (params->cfg_rx2tx_lp_en) | in sparx5_sd10g28_apply_params()
2020 (params->cfg_tx2rx_lp_en), in sparx5_sd10g28_apply_params()
2026 sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) | in sparx5_sd10g28_apply_params()
2027 SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en), in sparx5_sd10g28_apply_params()
2048 sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2053 sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2058 sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100), in sparx5_sd10g28_apply_params()
2069 return -EINVAL; in sparx5_sd10g28_apply_params()
2087 struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media]; in sparx5_sd25g28_config()
2103 sparx5_sd25g28_reset(macro->priv->regs, ¶ms, macro->stpidx); in sparx5_sd25g28_config()
2109 struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media]; in sparx5_sd10g28_config()
2113 .is_6g = (macro->serdestype == SPX5_SDT_6G), in sparx5_sd10g28_config()
2126 sparx5_sd10g28_reset(macro->priv->regs, macro->sidx); in sparx5_sd10g28_config()
2130 /* Power down serdes TX driver */
2133 struct sparx5_serdes_private *priv = macro->priv; in sparx5_serdes_power_save()
2136 if (macro->serdestype == SPX5_SDT_6G) in sparx5_serdes_power_save()
2137 sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx); in sparx5_serdes_power_save()
2138 else if (macro->serdestype == SPX5_SDT_10G) in sparx5_serdes_power_save()
2139 sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, macro->stpidx); in sparx5_serdes_power_save()
2141 sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx); in sparx5_serdes_power_save()
2143 if (macro->serdestype == SPX5_SDT_25G) { in sparx5_serdes_power_save()
2145 macro->stpidx); in sparx5_serdes_power_save()
2146 /* Take serdes out of reset */ in sparx5_serdes_power_save()
2162 sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE, macro->sidx); in sparx5_serdes_power_save()
2164 /* Take serdes out of reset */ in sparx5_serdes_power_save()
2184 struct sparx5_serdes_private *priv = macro->priv; in sparx5_serdes_clock_config()
2186 if (macro->serdesmode == SPX5_SD_MODE_100FX) { in sparx5_serdes_clock_config()
2187 u32 freq = priv->coreclock == 250000000 ? 2 : in sparx5_serdes_clock_config()
2188 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
2193 SD_LANE_MISC(macro->sidx)); in sparx5_serdes_clock_config()
2209 /* The same Serdes mode is used for both SGMII and 1000BaseX */ in sparx5_serdes_get_serdesmode()
2216 return -EINVAL; in sparx5_serdes_get_serdesmode()
2222 struct device *dev = macro->priv->dev; in sparx5_serdes_config()
2226 serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed); in sparx5_serdes_config()
2228 dev_err(dev, "SerDes %u, interface not supported: %s\n", in sparx5_serdes_config()
2229 macro->sidx, in sparx5_serdes_config()
2230 phy_modes(macro->portmode)); in sparx5_serdes_config()
2233 macro->serdesmode = serdesmode; in sparx5_serdes_config()
2237 if (macro->serdestype == SPX5_SDT_25G) in sparx5_serdes_config()
2242 dev_err(dev, "SerDes %u, config error: %d\n", in sparx5_serdes_config()
2243 macro->sidx, err); in sparx5_serdes_config()
2267 return -EINVAL; in sparx5_serdes_set_mode()
2276 macro->portmode = submode; in sparx5_serdes_set_mode()
2280 return -EINVAL; in sparx5_serdes_set_mode()
2288 if (media != macro->media) { in sparx5_serdes_set_media()
2289 macro->media = media; in sparx5_serdes_set_media()
2290 if (macro->serdesmode != SPX5_SD_MODE_NONE) in sparx5_serdes_set_media()
2300 if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) in sparx5_serdes_set_speed()
2301 return -EINVAL; in sparx5_serdes_set_speed()
2302 if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) in sparx5_serdes_set_speed()
2303 return -EINVAL; in sparx5_serdes_set_speed()
2304 if (speed != macro->speed) { in sparx5_serdes_set_speed()
2305 macro->speed = speed; in sparx5_serdes_set_speed()
2306 if (macro->serdesmode != SPX5_SD_MODE_NONE) in sparx5_serdes_set_speed()
2317 if (macro->serdestype == SPX5_SDT_25G) in sparx5_serdes_reset()
2322 dev_err(&phy->dev, "SerDes %u, reset error: %d\n", in sparx5_serdes_reset()
2323 macro->sidx, err); in sparx5_serdes_reset()
2335 return -EINVAL; in sparx5_serdes_validate()
2337 if (macro->speed == 0) in sparx5_serdes_validate()
2338 return -EINVAL; in sparx5_serdes_validate()
2340 if (macro->sidx < SPX5_SERDES_10G_START && macro->speed > SPEED_5000) in sparx5_serdes_validate()
2341 return -EINVAL; in sparx5_serdes_validate()
2342 if (macro->sidx < SPX5_SERDES_25G_START && macro->speed > SPEED_10000) in sparx5_serdes_validate()
2343 return -EINVAL; in sparx5_serdes_validate()
2347 if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ in sparx5_serdes_validate()
2348 macro->speed != SPEED_1000) in sparx5_serdes_validate()
2349 return -EINVAL; in sparx5_serdes_validate()
2354 if (macro->speed >= SPEED_5000) in sparx5_serdes_validate()
2355 return -EINVAL; in sparx5_serdes_validate()
2358 if (macro->speed < SPEED_5000) in sparx5_serdes_validate()
2359 return -EINVAL; in sparx5_serdes_validate()
2362 return -EINVAL; in sparx5_serdes_validate()
2383 *phy = devm_phy_create(priv->dev, NULL, &sparx5_serdes_ops); in sparx5_phy_create()
2387 macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL); in sparx5_phy_create()
2389 return -ENOMEM; in sparx5_phy_create()
2391 macro->sidx = idx; in sparx5_phy_create()
2392 macro->priv = priv; in sparx5_phy_create()
2393 macro->speed = SPEED_UNKNOWN; in sparx5_phy_create()
2395 macro->serdestype = SPX5_SDT_6G; in sparx5_phy_create()
2396 macro->stpidx = macro->sidx; in sparx5_phy_create()
2398 macro->serdestype = SPX5_SDT_10G; in sparx5_phy_create()
2399 macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; in sparx5_phy_create()
2401 macro->serdestype = SPX5_SDT_25G; in sparx5_phy_create()
2402 macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; in sparx5_phy_create()
2407 /* Power off serdes by default */ in sparx5_phy_create()
2510 /* Client lookup function, uses serdes index */
2518 if (args->args_count != 1) in sparx5_serdes_xlate()
2519 return ERR_PTR(-EINVAL); in sparx5_serdes_xlate()
2521 sidx = args->args[0]; in sparx5_serdes_xlate()
2523 /* Check validity: ERR_PTR(-ENODEV) if not valid */ in sparx5_serdes_xlate()
2526 phy_get_drvdata(priv->phys[idx]); in sparx5_serdes_xlate()
2528 if (sidx != macro->sidx) in sparx5_serdes_xlate()
2531 return priv->phys[idx]; in sparx5_serdes_xlate()
2533 return ERR_PTR(-ENODEV); in sparx5_serdes_xlate()
2538 struct device_node *np = pdev->dev.of_node; in sparx5_serdes_probe()
2544 struct clk *clk; in sparx5_serdes_probe() local
2548 if (!np && !pdev->dev.platform_data) in sparx5_serdes_probe()
2549 return -ENODEV; in sparx5_serdes_probe()
2551 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in sparx5_serdes_probe()
2553 return -ENOMEM; in sparx5_serdes_probe()
2556 priv->dev = &pdev->dev; in sparx5_serdes_probe()
2559 clk = devm_clk_get(priv->dev, NULL); in sparx5_serdes_probe()
2560 if (IS_ERR(clk)) { in sparx5_serdes_probe()
2561 dev_err(priv->dev, "Failed to get coreclock\n"); in sparx5_serdes_probe()
2562 return PTR_ERR(clk); in sparx5_serdes_probe()
2564 clock = clk_get_rate(clk); in sparx5_serdes_probe()
2566 dev_err(priv->dev, "Invalid coreclock %lu\n", clock); in sparx5_serdes_probe()
2567 return -EINVAL; in sparx5_serdes_probe()
2569 priv->coreclock = clock; in sparx5_serdes_probe()
2573 dev_err(priv->dev, "Invalid resource\n"); in sparx5_serdes_probe()
2574 return -EINVAL; in sparx5_serdes_probe()
2576 iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); in sparx5_serdes_probe()
2578 dev_err(priv->dev, "Unable to get serdes registers: %s\n", in sparx5_serdes_probe()
2579 iores->name); in sparx5_serdes_probe()
2580 return -ENOMEM; in sparx5_serdes_probe()
2585 priv->regs[iomap->id] = iomem + iomap->offset; in sparx5_serdes_probe()
2588 err = sparx5_phy_create(priv, idx, &priv->phys[idx]); in sparx5_serdes_probe()
2596 provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); in sparx5_serdes_probe()
2602 { .compatible = "microchip,sparx5-serdes" },
2610 .name = "sparx5-serdes",
2617 MODULE_DESCRIPTION("Microchip Sparx5 switch serdes driver");