309 	void __iomem *phya; /* include u3phya_da */  member
532 		tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);  in u3_phy_params_show()
586 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,  in u3_phy_params_write()
757 	void __iomem *phya = u3_banks->phya;  in u3_phy_instance_init()  local
782 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2);  in u3_phy_instance_init()
784 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4);  in u3_phy_instance_init()
786 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe);  in u3_phy_instance_init()
955 	void __iomem *phya = u3_banks->phya;  in pcie_phy_instance_init()  local
960 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,  in pcie_phy_instance_init()
966 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4);  in pcie_phy_instance_init()
968 	mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1);  in pcie_phy_instance_init()
971 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c);  in pcie_phy_instance_init()
973 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36);  in pcie_phy_instance_init()
976 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5,  in pcie_phy_instance_init()
981 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4,  in pcie_phy_instance_init()
985 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2);  in pcie_phy_instance_init()
987 	mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa);  in pcie_phy_instance_init()
1088 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
1116 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
1355 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,  in phy_efuse_set()