1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
13 #include <linux/mfd/syscon.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
218 /* CDR Charge Pump P-path current adjustment */
237 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
246 /* I-path capacitance adjustment for Gen1 */
279  * mtk_phy_pdata - SoC specific platform data
281  * @sw_pll_48m_to_26m:        Workaround for V3 IP (MT8195) - switch the 48MHz PLL from
283  * @sw_efuse_supported:       Switches off eFuse auto-load from PHY and applies values
284  *                            read from different nvmem (usually different eFuse array)
370 	[U2P_EFUSE_EN] = "efuse",
377 	[U3P_EFUSE_EN] = "efuse",
379 	[U3P_EFUSE_TX_IMP] = "tx-imp",
380 	[U3P_EFUSE_RX_IMP] = "rx-imp",
385 	struct mtk_phy_instance *inst = sf->private;  in u2_phy_params_show()
386 	struct u2phy_banks *u2_banks = &inst->u2_banks;  in u2_phy_params_show()
387 	void __iomem *com = u2_banks->com;  in u2_phy_params_show()
391 	int ret = debugfs_get_aux_num(sf->file);  in u2_phy_params_show()
407 		if (u2_banks->misc) {  in u2_phy_params_show()
408 			tmp = readl(u2_banks->misc + U3P_MISC_REG1);  in u2_phy_params_show()
445 	return single_open(file, u2_phy_params_show, inode->i_private);  in u2_phy_params_open()
451 	struct seq_file *sf = file->private_data;  in u2_phy_params_write()
452 	struct mtk_phy_instance *inst = sf->private;  in u2_phy_params_write()
453 	struct u2phy_banks *u2_banks = &inst->u2_banks;  in u2_phy_params_write()
454 	void __iomem *com = u2_banks->com;  in u2_phy_params_write()
473 		if (u2_banks->misc)  in u2_phy_params_write()
474 			mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1,  in u2_phy_params_write()
511 		debugfs_create_file_aux_num(u2_phy_files[i], 0644, inst->phy->debugfs,  in u2_phy_dbgfs_files_create()
517 	struct mtk_phy_instance *inst = sf->private;  in u3_phy_params_show()
518 	struct u3phy_banks *u3_banks = &inst->u3_banks;  in u3_phy_params_show()
522 	int ret = debugfs_get_aux_num(sf->file);  in u3_phy_params_show()
526 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);  in u3_phy_params_show()
532 		tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);  in u3_phy_params_show()
538 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);  in u3_phy_params_show()
544 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);  in u3_phy_params_show()
561 	return single_open(file, u3_phy_params_show, inode->i_private);  in u3_phy_params_open()
567 	struct seq_file *sf = file->private_data;  in u3_phy_params_write()
568 	struct mtk_phy_instance *inst = sf->private;  in u3_phy_params_write()
569 	struct u3phy_banks *u3_banks = &inst->u3_banks;  in u3_phy_params_write()
570 	void __iomem *phyd = u3_banks->phyd;  in u3_phy_params_write()
573 	int ret = debugfs_get_aux_num(sf->file);  in u3_phy_params_write()
586 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,  in u3_phy_params_write()
621 		debugfs_create_file_aux_num(u3_phy_files[i], 0644, inst->phy->debugfs,  in u3_phy_dbgfs_files_create()
627 	struct mtk_phy_instance *inst = sf->private;  in phy_type_show()
630 	switch (inst->type) {  in phy_type_show()
659 	debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops);  in phy_debugfs_init()
661 	switch (inst->type) {  in phy_debugfs_init()
684 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in hs_slew_rate_calibrate()
685 	void __iomem *fmreg = u2_banks->fmreg;  in hs_slew_rate_calibrate()
686 	void __iomem *com = u2_banks->com;  in hs_slew_rate_calibrate()
698 	if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef)  in hs_slew_rate_calibrate()
712 	if (tphy->pdata->version == MTK_PHY_V1)  in hs_slew_rate_calibrate()
713 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);  in hs_slew_rate_calibrate()
734 		tmp = tphy->src_ref_clk * tphy->src_coef;  in hs_slew_rate_calibrate()
741 	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in hs_slew_rate_calibrate()
742 		instance->index, fm_out, calibration_val,  in hs_slew_rate_calibrate()
743 		tphy->src_ref_clk, tphy->src_coef);  in hs_slew_rate_calibrate()
756 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in u3_phy_instance_init()
757 	void __iomem *phya = u3_banks->phya;  in u3_phy_instance_init()
758 	void __iomem *phyd = u3_banks->phyd;  in u3_phy_instance_init()
760 	if (instance->type_force_mode) {  in u3_phy_instance_init()
765 		mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,  in u3_phy_instance_init()
767 		mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,  in u3_phy_instance_init()
771 		mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,  in u3_phy_instance_init()
773 		mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,  in u3_phy_instance_init()
778 	mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,  in u3_phy_instance_init()
788 	mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,  in u3_phy_instance_init()
799 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in u3_phy_instance_init()
805 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_pll_26m_set()
806 	void __iomem *com = u2_banks->com;  in u2_phy_pll_26m_set()
808 	if (!tphy->pdata->sw_pll_48m_to_26m)  in u2_phy_pll_26m_set()
824 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_init()
825 	void __iomem *com = u2_banks->com;  in u2_phy_instance_init()
826 	u32 index = instance->index;  in u2_phy_instance_init()
843 	if (tphy->pdata->avoid_rx_sen_degradation) {  in u2_phy_instance_init()
864 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_init()
870 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_on()
871 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_on()
872 	u32 index = instance->index;  in u2_phy_instance_power_on()
881 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_on()
886 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
892 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_off()
893 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_off()
894 	u32 index = instance->index;  in u2_phy_instance_power_off()
903 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_off()
909 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
915 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_exit()
916 	void __iomem *com = u2_banks->com;  in u2_phy_instance_exit()
917 	u32 index = instance->index;  in u2_phy_instance_exit()
919 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_exit()
930 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_set_mode()
933 	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
948 	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
954 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in pcie_phy_instance_init()
955 	void __iomem *phya = u3_banks->phya;  in pcie_phy_instance_init()
957 	if (tphy->pdata->version != MTK_PHY_V1)  in pcie_phy_instance_init()
970 	/* SSC delta -5000ppm */  in pcie_phy_instance_init()
989 	/* Tx Detect Rx Timing: 10us -> 5us */  in pcie_phy_instance_init()
990 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,  in pcie_phy_instance_init()
993 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,  in pcie_phy_instance_init()
998 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in pcie_phy_instance_init()
1004 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_on()
1006 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,  in pcie_phy_instance_power_on()
1009 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,  in pcie_phy_instance_power_on()
1017 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_off()
1019 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,  in pcie_phy_instance_power_off()
1022 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,  in pcie_phy_instance_power_off()
1029 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in sata_phy_instance_init()
1030 	void __iomem *phyd = u3_banks->phyd;  in sata_phy_instance_init()
1068 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in sata_phy_instance_init()
1074 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v1_banks_init()
1075 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v1_banks_init()
1077 	switch (instance->type) {  in phy_v1_banks_init()
1079 		u2_banks->misc = NULL;  in phy_v1_banks_init()
1080 		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;  in phy_v1_banks_init()
1081 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;  in phy_v1_banks_init()
1085 		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;  in phy_v1_banks_init()
1086 		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;  in phy_v1_banks_init()
1087 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1088 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
1091 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1094 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v1_banks_init()
1102 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v2_banks_init()
1103 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v2_banks_init()
1105 	switch (instance->type) {  in phy_v2_banks_init()
1107 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;  in phy_v2_banks_init()
1108 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;  in phy_v2_banks_init()
1109 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;  in phy_v2_banks_init()
1113 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;  in phy_v2_banks_init()
1114 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;  in phy_v2_banks_init()
1115 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;  in phy_v2_banks_init()
1116 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
1119 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v2_banks_init()
1127 	struct device *dev = &instance->phy->dev;  in phy_parse_property()
1129 	if (instance->type == PHY_TYPE_USB3)  in phy_parse_property()
1130 		instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");  in phy_parse_property()
1132 	if (instance->type != PHY_TYPE_USB2)  in phy_parse_property()
1135 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");  in phy_parse_property()
1136 	device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
1137 				 &instance->eye_src);  in phy_parse_property()
1138 	device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
1139 				 &instance->eye_vrt);  in phy_parse_property()
1140 	device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
1141 				 &instance->eye_term);  in phy_parse_property()
1143 				 &instance->intr);  in phy_parse_property()
1145 				 &instance->discth);  in phy_parse_property()
1146 	device_property_read_u32(dev, "mediatek,pre-emphasis",  in phy_parse_property()
1147 				 &instance->pre_emphasis);  in phy_parse_property()
1149 		instance->bc12_en, instance->eye_src,  in phy_parse_property()
1150 		instance->eye_vrt, instance->eye_term,  in phy_parse_property()
1151 		instance->intr, instance->discth);  in phy_parse_property()
1152 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);  in phy_parse_property()
1158 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_props_set()
1159 	void __iomem *com = u2_banks->com;  in u2_phy_props_set()
1161 	if (instance->bc12_en) /* BC1.2 path Enable */  in u2_phy_props_set()
1164 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)  in u2_phy_props_set()
1166 				     instance->eye_src);  in u2_phy_props_set()
1168 	if (instance->eye_vrt)  in u2_phy_props_set()
1170 				     instance->eye_vrt);  in u2_phy_props_set()
1172 	if (instance->eye_term)  in u2_phy_props_set()
1174 				     instance->eye_term);  in u2_phy_props_set()
1176 	if (instance->intr) {  in u2_phy_props_set()
1177 		if (u2_banks->misc)  in u2_phy_props_set()
1178 			mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,  in u2_phy_props_set()
1182 				     instance->intr);  in u2_phy_props_set()
1185 	if (instance->discth)  in u2_phy_props_set()
1187 				     instance->discth);  in u2_phy_props_set()
1189 	if (instance->pre_emphasis)  in u2_phy_props_set()
1191 				     instance->pre_emphasis);  in u2_phy_props_set()
1202 	if (!of_property_present(dn, "mediatek,syscon-type"))  in phy_type_syscon_get()
1205 	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",  in phy_type_syscon_get()
1210 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
1211 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
1212 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
1214 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
1215 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
1217 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
1225 	if (!instance->type_sw)  in phy_type_set()
1228 	switch (instance->type) {  in phy_type_set()
1246 	offset = instance->type_sw_index * BITS_PER_BYTE;  in phy_type_set()
1247 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,  in phy_type_set()
1255 	struct device *dev = &instance->phy->dev;  in phy_efuse_get()
1258 	/* tphy v1 doesn't support sw efuse, skip it */  in phy_efuse_get()
1259 	if (!tphy->pdata->sw_efuse_supported) {  in phy_efuse_get()
1260 		instance->efuse_sw_en = 0;  in phy_efuse_get()
1264 	/* software efuse is optional */  in phy_efuse_get()
1265 	instance->efuse_sw_en = device_property_present(dev, "nvmem-cells");  in phy_efuse_get()
1266 	if (!instance->efuse_sw_en)  in phy_efuse_get()
1269 	switch (instance->type) {  in phy_efuse_get()
1271 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1273 			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);  in phy_efuse_get()
1277 		/* no efuse, ignore it */  in phy_efuse_get()
1278 		if (!instance->efuse_intr) {  in phy_efuse_get()
1279 			dev_warn(dev, "no u2 intr efuse, but dts enable it\n");  in phy_efuse_get()
1280 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1284 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);  in phy_efuse_get()
1289 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1291 			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);  in phy_efuse_get()
1295 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);  in phy_efuse_get()
1297 			dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret);  in phy_efuse_get()
1301 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);  in phy_efuse_get()
1303 			dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret);  in phy_efuse_get()
1307 		/* no efuse, ignore it */  in phy_efuse_get()
1308 		if (!instance->efuse_intr &&  in phy_efuse_get()
1309 		    !instance->efuse_rx_imp &&  in phy_efuse_get()
1310 		    !instance->efuse_tx_imp) {  in phy_efuse_get()
1311 			dev_warn(dev, "no u3 intr efuse, but dts enable it\n");  in phy_efuse_get()
1312 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1316 		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",  in phy_efuse_get()
1317 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);  in phy_efuse_get()
1320 		dev_err(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_get()
1321 		ret = -EINVAL;  in phy_efuse_get()
1329 	struct device *dev = &instance->phy->dev;  in phy_efuse_set()
1330 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_efuse_set()
1331 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_efuse_set()
1333 	if (!instance->efuse_sw_en)  in phy_efuse_set()
1336 	switch (instance->type) {  in phy_efuse_set()
1338 		mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);  in phy_efuse_set()
1340 		mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,  in phy_efuse_set()
1341 				     instance->efuse_intr);  in phy_efuse_set()
1345 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);  in phy_efuse_set()
1347 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,  in phy_efuse_set()
1348 				    instance->efuse_tx_imp);  in phy_efuse_set()
1349 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);  in phy_efuse_set()
1351 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,  in phy_efuse_set()
1352 				    instance->efuse_rx_imp);  in phy_efuse_set()
1353 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);  in phy_efuse_set()
1355 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,  in phy_efuse_set()
1356 				    instance->efuse_intr);  in phy_efuse_set()
1359 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_set()
1367 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
1370 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1376 	switch (instance->type) {  in mtk_phy_init()
1394 		dev_err(tphy->dev, "incompatible PHY type\n");  in mtk_phy_init()
1395 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1396 		return -EINVAL;  in mtk_phy_init()
1405 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
1407 	if (instance->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
1410 	} else if (instance->type == PHY_TYPE_PCIE) {  in mtk_phy_power_on()
1420 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
1422 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
1424 	else if (instance->type == PHY_TYPE_PCIE)  in mtk_phy_power_off()
1433 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_exit()
1435 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_exit()
1438 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_exit()
1445 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
1447 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
1458 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
1462 	if (args->args_count != 1) {  in mtk_phy_xlate()
1464 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1467 	for (index = 0; index < tphy->nphys; index++)  in mtk_phy_xlate()
1468 		if (phy_np == tphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
1469 			instance = tphy->phys[index];  in mtk_phy_xlate()
1475 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1478 	instance->type = args->args[0];  in mtk_phy_xlate()
1479 	if (!(instance->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
1480 	      instance->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
1481 	      instance->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
1482 	      instance->type == PHY_TYPE_SATA ||  in mtk_phy_xlate()
1483 	      instance->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
1484 		dev_err(dev, "unsupported device type: %d\n", instance->type);  in mtk_phy_xlate()
1485 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1488 	switch (tphy->pdata->version) {  in mtk_phy_xlate()
1498 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1509 	return instance->phy;  in mtk_phy_xlate()
1555 	{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1556 	{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1557 	{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1558 	{ .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1559 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1560 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1561 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1568 	struct device *dev = &pdev->dev;  in mtk_tphy_probe()
1569 	struct device_node *np = dev->of_node;  in mtk_tphy_probe()
1578 		return -ENOMEM;  in mtk_tphy_probe()
1580 	tphy->pdata = of_device_get_match_data(dev);  in mtk_tphy_probe()
1581 	if (!tphy->pdata)  in mtk_tphy_probe()
1582 		return -EINVAL;  in mtk_tphy_probe()
1584 	tphy->nphys = of_get_child_count(np);  in mtk_tphy_probe()
1585 	tphy->phys = devm_kcalloc(dev, tphy->nphys,  in mtk_tphy_probe()
1586 				       sizeof(*tphy->phys), GFP_KERNEL);  in mtk_tphy_probe()
1587 	if (!tphy->phys)  in mtk_tphy_probe()
1588 		return -ENOMEM;  in mtk_tphy_probe()
1590 	tphy->dev = dev;  in mtk_tphy_probe()
1595 	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {  in mtk_tphy_probe()
1597 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);  in mtk_tphy_probe()
1598 		if (IS_ERR(tphy->sif_base)) {  in mtk_tphy_probe()
1600 			return PTR_ERR(tphy->sif_base);  in mtk_tphy_probe()
1605 	ret = device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", &tphy->src_ref_clk);  in mtk_tphy_probe()
1607 		tphy->src_ref_clk = tphy->pdata->slew_ref_clock_mhz;  in mtk_tphy_probe()
1609 	ret = device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);  in mtk_tphy_probe()
1611 		tphy->src_coef = tphy->pdata->slew_rate_coefficient;  in mtk_tphy_probe()
1623 			return -ENOMEM;  in mtk_tphy_probe()
1625 		tphy->phys[port] = instance;  in mtk_tphy_probe()
1633 		subdev = &phy->dev;  in mtk_tphy_probe()
1636 			dev_err(subdev, "failed to get address resource(id-%d)\n",  in mtk_tphy_probe()
1641 		instance->port_base = devm_ioremap_resource(subdev, &res);  in mtk_tphy_probe()
1642 		if (IS_ERR(instance->port_base))  in mtk_tphy_probe()
1643 			return PTR_ERR(instance->port_base);  in mtk_tphy_probe()
1645 		instance->phy = phy;  in mtk_tphy_probe()
1646 		instance->index = port;  in mtk_tphy_probe()
1650 		clks = instance->clks;  in mtk_tphy_probe()
1670 		.name	= "mtk-tphy",
1678 MODULE_DESCRIPTION("MediaTek T-PHY driver");