1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
220 /* CDR Charge Pump P-path current adjustment */
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
248 /* I-path capacitance adjustment for Gen1 */
284 	 * workaround only for mt8195, HW fix it for others of V3,
290 	 * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
368 	[U2P_EFUSE_EN] = "efuse",
375 	[U3P_EFUSE_EN] = "efuse",
377 	[U3P_EFUSE_TX_IMP] = "tx-imp",
378 	[U3P_EFUSE_RX_IMP] = "rx-imp",
383 	struct mtk_phy_instance *inst = sf->private;  in u2_phy_params_show()
384 	const char *fname = file_dentry(sf->file)->d_iname;  in u2_phy_params_show()
385 	struct u2phy_banks *u2_banks = &inst->u2_banks;  in u2_phy_params_show()
386 	void __iomem *com = u2_banks->com;  in u2_phy_params_show()
410 		if (u2_banks->misc) {  in u2_phy_params_show()
411 			tmp = readl(u2_banks->misc + U3P_MISC_REG1);  in u2_phy_params_show()
448 	return single_open(file, u2_phy_params_show, inode->i_private);  in u2_phy_params_open()
454 	const char *fname = file_dentry(file)->d_iname;  in u2_phy_params_write()
455 	struct seq_file *sf = file->private_data;  in u2_phy_params_write()
456 	struct mtk_phy_instance *inst = sf->private;  in u2_phy_params_write()
457 	struct u2phy_banks *u2_banks = &inst->u2_banks;  in u2_phy_params_write()
458 	void __iomem *com = u2_banks->com;  in u2_phy_params_write()
481 		if (u2_banks->misc)  in u2_phy_params_write()
482 			mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1,  in u2_phy_params_write()
519 		debugfs_create_file(u2_phy_files[i], 0644, inst->phy->debugfs,  in u2_phy_dbgfs_files_create()
525 	struct mtk_phy_instance *inst = sf->private;  in u3_phy_params_show()
526 	const char *fname = file_dentry(sf->file)->d_iname;  in u3_phy_params_show()
527 	struct u3phy_banks *u3_banks = &inst->u3_banks;  in u3_phy_params_show()
539 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);  in u3_phy_params_show()
545 		tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);  in u3_phy_params_show()
551 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);  in u3_phy_params_show()
557 		tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);  in u3_phy_params_show()
574 	return single_open(file, u3_phy_params_show, inode->i_private);  in u3_phy_params_open()
580 	const char *fname = file_dentry(file)->d_iname;  in u3_phy_params_write()
581 	struct seq_file *sf = file->private_data;  in u3_phy_params_write()
582 	struct mtk_phy_instance *inst = sf->private;  in u3_phy_params_write()
583 	struct u3phy_banks *u3_banks = &inst->u3_banks;  in u3_phy_params_write()
584 	void __iomem *phyd = u3_banks->phyd;  in u3_phy_params_write()
604 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,  in u3_phy_params_write()
639 		debugfs_create_file(u3_phy_files[i], 0644, inst->phy->debugfs,  in u3_phy_dbgfs_files_create()
645 	struct mtk_phy_instance *inst = sf->private;  in phy_type_show()
648 	switch (inst->type) {  in phy_type_show()
677 	debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops);  in phy_debugfs_init()
679 	switch (inst->type) {  in phy_debugfs_init()
702 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in hs_slew_rate_calibrate()
703 	void __iomem *fmreg = u2_banks->fmreg;  in hs_slew_rate_calibrate()
704 	void __iomem *com = u2_banks->com;  in hs_slew_rate_calibrate()
710 	if (tphy->pdata->version == MTK_PHY_V3)  in hs_slew_rate_calibrate()
714 	if (instance->eye_src)  in hs_slew_rate_calibrate()
728 	if (tphy->pdata->version == MTK_PHY_V1)  in hs_slew_rate_calibrate()
729 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);  in hs_slew_rate_calibrate()
750 		tmp = tphy->src_ref_clk * tphy->src_coef;  in hs_slew_rate_calibrate()
757 	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in hs_slew_rate_calibrate()
758 		instance->index, fm_out, calibration_val,  in hs_slew_rate_calibrate()
759 		tphy->src_ref_clk, tphy->src_coef);  in hs_slew_rate_calibrate()
772 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in u3_phy_instance_init()
773 	void __iomem *phya = u3_banks->phya;  in u3_phy_instance_init()
774 	void __iomem *phyd = u3_banks->phyd;  in u3_phy_instance_init()
776 	if (instance->type_force_mode) {  in u3_phy_instance_init()
781 		mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,  in u3_phy_instance_init()
783 		mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,  in u3_phy_instance_init()
787 		mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,  in u3_phy_instance_init()
789 		mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,  in u3_phy_instance_init()
794 	mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,  in u3_phy_instance_init()
804 	mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,  in u3_phy_instance_init()
815 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in u3_phy_instance_init()
821 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_pll_26m_set()
822 	void __iomem *com = u2_banks->com;  in u2_phy_pll_26m_set()
824 	if (!tphy->pdata->sw_pll_48m_to_26m)  in u2_phy_pll_26m_set()
840 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_init()
841 	void __iomem *com = u2_banks->com;  in u2_phy_instance_init()
842 	u32 index = instance->index;  in u2_phy_instance_init()
859 	if (tphy->pdata->avoid_rx_sen_degradation) {  in u2_phy_instance_init()
877 	/* Workaround only for mt8195, HW fix it for others (V3) */  in u2_phy_instance_init()
880 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_init()
886 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_on()
887 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_on()
888 	u32 index = instance->index;  in u2_phy_instance_power_on()
897 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_on()
902 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
908 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_off()
909 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_off()
910 	u32 index = instance->index;  in u2_phy_instance_power_off()
919 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_off()
925 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
931 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_exit()
932 	void __iomem *com = u2_banks->com;  in u2_phy_instance_exit()
933 	u32 index = instance->index;  in u2_phy_instance_exit()
935 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_exit()
946 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_set_mode()
949 	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
964 	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
970 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in pcie_phy_instance_init()
971 	void __iomem *phya = u3_banks->phya;  in pcie_phy_instance_init()
973 	if (tphy->pdata->version != MTK_PHY_V1)  in pcie_phy_instance_init()
986 	/* SSC delta -5000ppm */  in pcie_phy_instance_init()
1005 	/* Tx Detect Rx Timing: 10us -> 5us */  in pcie_phy_instance_init()
1006 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,  in pcie_phy_instance_init()
1009 	mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,  in pcie_phy_instance_init()
1014 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in pcie_phy_instance_init()
1020 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_on()
1022 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,  in pcie_phy_instance_power_on()
1025 	mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,  in pcie_phy_instance_power_on()
1033 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_off()
1035 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,  in pcie_phy_instance_power_off()
1038 	mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,  in pcie_phy_instance_power_off()
1045 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in sata_phy_instance_init()
1046 	void __iomem *phyd = u3_banks->phyd;  in sata_phy_instance_init()
1084 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in sata_phy_instance_init()
1090 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v1_banks_init()
1091 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v1_banks_init()
1093 	switch (instance->type) {  in phy_v1_banks_init()
1095 		u2_banks->misc = NULL;  in phy_v1_banks_init()
1096 		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;  in phy_v1_banks_init()
1097 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;  in phy_v1_banks_init()
1101 		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;  in phy_v1_banks_init()
1102 		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;  in phy_v1_banks_init()
1103 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1104 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
1107 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1110 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v1_banks_init()
1118 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v2_banks_init()
1119 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v2_banks_init()
1121 	switch (instance->type) {  in phy_v2_banks_init()
1123 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;  in phy_v2_banks_init()
1124 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;  in phy_v2_banks_init()
1125 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;  in phy_v2_banks_init()
1129 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;  in phy_v2_banks_init()
1130 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;  in phy_v2_banks_init()
1131 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;  in phy_v2_banks_init()
1132 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
1135 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v2_banks_init()
1143 	struct device *dev = &instance->phy->dev;  in phy_parse_property()
1145 	if (instance->type == PHY_TYPE_USB3)  in phy_parse_property()
1146 		instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");  in phy_parse_property()
1148 	if (instance->type != PHY_TYPE_USB2)  in phy_parse_property()
1151 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");  in phy_parse_property()
1152 	device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
1153 				 &instance->eye_src);  in phy_parse_property()
1154 	device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
1155 				 &instance->eye_vrt);  in phy_parse_property()
1156 	device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
1157 				 &instance->eye_term);  in phy_parse_property()
1159 				 &instance->intr);  in phy_parse_property()
1161 				 &instance->discth);  in phy_parse_property()
1162 	device_property_read_u32(dev, "mediatek,pre-emphasis",  in phy_parse_property()
1163 				 &instance->pre_emphasis);  in phy_parse_property()
1165 		instance->bc12_en, instance->eye_src,  in phy_parse_property()
1166 		instance->eye_vrt, instance->eye_term,  in phy_parse_property()
1167 		instance->intr, instance->discth);  in phy_parse_property()
1168 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);  in phy_parse_property()
1174 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_props_set()
1175 	void __iomem *com = u2_banks->com;  in u2_phy_props_set()
1177 	if (instance->bc12_en) /* BC1.2 path Enable */  in u2_phy_props_set()
1180 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)  in u2_phy_props_set()
1182 				     instance->eye_src);  in u2_phy_props_set()
1184 	if (instance->eye_vrt)  in u2_phy_props_set()
1186 				     instance->eye_vrt);  in u2_phy_props_set()
1188 	if (instance->eye_term)  in u2_phy_props_set()
1190 				     instance->eye_term);  in u2_phy_props_set()
1192 	if (instance->intr) {  in u2_phy_props_set()
1193 		if (u2_banks->misc)  in u2_phy_props_set()
1194 			mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,  in u2_phy_props_set()
1198 				     instance->intr);  in u2_phy_props_set()
1201 	if (instance->discth)  in u2_phy_props_set()
1203 				     instance->discth);  in u2_phy_props_set()
1205 	if (instance->pre_emphasis)  in u2_phy_props_set()
1207 				     instance->pre_emphasis);  in u2_phy_props_set()
1218 	if (!of_property_read_bool(dn, "mediatek,syscon-type"))  in phy_type_syscon_get()
1221 	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",  in phy_type_syscon_get()
1226 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
1227 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
1228 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
1230 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
1231 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
1233 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
1241 	if (!instance->type_sw)  in phy_type_set()
1244 	switch (instance->type) {  in phy_type_set()
1262 	offset = instance->type_sw_index * BITS_PER_BYTE;  in phy_type_set()
1263 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,  in phy_type_set()
1271 	struct device *dev = &instance->phy->dev;  in phy_efuse_get()
1274 	/* tphy v1 doesn't support sw efuse, skip it */  in phy_efuse_get()
1275 	if (!tphy->pdata->sw_efuse_supported) {  in phy_efuse_get()
1276 		instance->efuse_sw_en = 0;  in phy_efuse_get()
1280 	/* software efuse is optional */  in phy_efuse_get()
1281 	instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");  in phy_efuse_get()
1282 	if (!instance->efuse_sw_en)  in phy_efuse_get()
1285 	switch (instance->type) {  in phy_efuse_get()
1287 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1289 			dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);  in phy_efuse_get()
1293 		/* no efuse, ignore it */  in phy_efuse_get()
1294 		if (!instance->efuse_intr) {  in phy_efuse_get()
1295 			dev_warn(dev, "no u2 intr efuse, but dts enable it\n");  in phy_efuse_get()
1296 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1300 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);  in phy_efuse_get()
1305 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1307 			dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);  in phy_efuse_get()
1311 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);  in phy_efuse_get()
1313 			dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret);  in phy_efuse_get()
1317 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);  in phy_efuse_get()
1319 			dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret);  in phy_efuse_get()
1323 		/* no efuse, ignore it */  in phy_efuse_get()
1324 		if (!instance->efuse_intr &&  in phy_efuse_get()
1325 		    !instance->efuse_rx_imp &&  in phy_efuse_get()
1326 		    !instance->efuse_tx_imp) {  in phy_efuse_get()
1327 			dev_warn(dev, "no u3 intr efuse, but dts enable it\n");  in phy_efuse_get()
1328 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1332 		dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",  in phy_efuse_get()
1333 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);  in phy_efuse_get()
1336 		dev_err(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_get()
1337 		ret = -EINVAL;  in phy_efuse_get()
1345 	struct device *dev = &instance->phy->dev;  in phy_efuse_set()
1346 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_efuse_set()
1347 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_efuse_set()
1349 	if (!instance->efuse_sw_en)  in phy_efuse_set()
1352 	switch (instance->type) {  in phy_efuse_set()
1354 		mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);  in phy_efuse_set()
1356 		mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,  in phy_efuse_set()
1357 				     instance->efuse_intr);  in phy_efuse_set()
1361 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);  in phy_efuse_set()
1363 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,  in phy_efuse_set()
1364 				    instance->efuse_tx_imp);  in phy_efuse_set()
1365 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);  in phy_efuse_set()
1367 		mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,  in phy_efuse_set()
1368 				    instance->efuse_rx_imp);  in phy_efuse_set()
1369 		mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);  in phy_efuse_set()
1371 		mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,  in phy_efuse_set()
1372 				    instance->efuse_intr);  in phy_efuse_set()
1375 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_set()
1383 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
1386 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1392 	switch (instance->type) {  in mtk_phy_init()
1410 		dev_err(tphy->dev, "incompatible PHY type\n");  in mtk_phy_init()
1411 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1412 		return -EINVAL;  in mtk_phy_init()
1421 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
1423 	if (instance->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
1426 	} else if (instance->type == PHY_TYPE_PCIE) {  in mtk_phy_power_on()
1436 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
1438 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
1440 	else if (instance->type == PHY_TYPE_PCIE)  in mtk_phy_power_off()
1449 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_exit()
1451 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_exit()
1454 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_exit()
1461 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
1463 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
1474 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
1478 	if (args->args_count != 1) {  in mtk_phy_xlate()
1480 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1483 	for (index = 0; index < tphy->nphys; index++)  in mtk_phy_xlate()
1484 		if (phy_np == tphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
1485 			instance = tphy->phys[index];  in mtk_phy_xlate()
1491 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1494 	instance->type = args->args[0];  in mtk_phy_xlate()
1495 	if (!(instance->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
1496 	      instance->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
1497 	      instance->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
1498 	      instance->type == PHY_TYPE_SATA ||  in mtk_phy_xlate()
1499 	      instance->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
1500 		dev_err(dev, "unsupported device type: %d\n", instance->type);  in mtk_phy_xlate()
1501 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1504 	switch (tphy->pdata->version) {  in mtk_phy_xlate()
1514 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1525 	return instance->phy;  in mtk_phy_xlate()
1565 	{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1566 	{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1567 	{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1568 	{ .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1569 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1570 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1571 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1578 	struct device *dev = &pdev->dev;  in mtk_tphy_probe()
1579 	struct device_node *np = dev->of_node;  in mtk_tphy_probe()
1588 		return -ENOMEM;  in mtk_tphy_probe()
1590 	tphy->pdata = of_device_get_match_data(dev);  in mtk_tphy_probe()
1591 	if (!tphy->pdata)  in mtk_tphy_probe()
1592 		return -EINVAL;  in mtk_tphy_probe()
1594 	tphy->nphys = of_get_child_count(np);  in mtk_tphy_probe()
1595 	tphy->phys = devm_kcalloc(dev, tphy->nphys,  in mtk_tphy_probe()
1596 				       sizeof(*tphy->phys), GFP_KERNEL);  in mtk_tphy_probe()
1597 	if (!tphy->phys)  in mtk_tphy_probe()
1598 		return -ENOMEM;  in mtk_tphy_probe()
1600 	tphy->dev = dev;  in mtk_tphy_probe()
1605 	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {  in mtk_tphy_probe()
1607 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);  in mtk_tphy_probe()
1608 		if (IS_ERR(tphy->sif_base)) {  in mtk_tphy_probe()
1610 			return PTR_ERR(tphy->sif_base);  in mtk_tphy_probe()
1614 	if (tphy->pdata->version < MTK_PHY_V3) {  in mtk_tphy_probe()
1615 		tphy->src_ref_clk = U3P_REF_CLK;  in mtk_tphy_probe()
1616 		tphy->src_coef = U3P_SLEW_RATE_COEF;  in mtk_tphy_probe()
1618 		device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",  in mtk_tphy_probe()
1619 					 &tphy->src_ref_clk);  in mtk_tphy_probe()
1620 		device_property_read_u32(dev, "mediatek,src-coef",  in mtk_tphy_probe()
1621 					 &tphy->src_coef);  in mtk_tphy_probe()
1634 			return -ENOMEM;  in mtk_tphy_probe()
1636 		tphy->phys[port] = instance;  in mtk_tphy_probe()
1644 		subdev = &phy->dev;  in mtk_tphy_probe()
1647 			dev_err(subdev, "failed to get address resource(id-%d)\n",  in mtk_tphy_probe()
1652 		instance->port_base = devm_ioremap_resource(subdev, &res);  in mtk_tphy_probe()
1653 		if (IS_ERR(instance->port_base))  in mtk_tphy_probe()
1654 			return PTR_ERR(instance->port_base);  in mtk_tphy_probe()
1656 		instance->phy = phy;  in mtk_tphy_probe()
1657 		instance->index = port;  in mtk_tphy_probe()
1661 		clks = instance->clks;  in mtk_tphy_probe()
1681 		.name	= "mtk-tphy",
1689 MODULE_DESCRIPTION("MediaTek T-PHY driver");