Lines Matching +full:eye +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
220 /* CDR Charge Pump P-path current adjustment */
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
248 /* I-path capacitance adjustment for Gen1 */
377 [U3P_EFUSE_TX_IMP] = "tx-imp",
378 [U3P_EFUSE_RX_IMP] = "rx-imp",
383 struct mtk_phy_instance *inst = sf->private;
384 struct u2phy_banks *u2_banks = &inst->u2_banks;
385 void __iomem *com = u2_banks->com;
389 int ret = debugfs_get_aux_num(sf->file);
405 if (u2_banks->misc) {
406 tmp = readl(u2_banks->misc + U3P_MISC_REG1);
443 return single_open(file, u2_phy_params_show, inode->i_private);
449 struct seq_file *sf = file->private_data;
450 struct mtk_phy_instance *inst = sf->private;
451 struct u2phy_banks *u2_banks = &inst->u2_banks;
452 void __iomem *com = u2_banks->com;
471 if (u2_banks->misc)
472 mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1,
509 debugfs_create_file_aux_num(u2_phy_files[i], 0644, inst->phy->debugfs,
515 struct mtk_phy_instance *inst = sf->private;
516 struct u3phy_banks *u3_banks = &inst->u3_banks;
520 int ret = debugfs_get_aux_num(sf->file);
524 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
530 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
536 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
542 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
559 return single_open(file, u3_phy_params_show, inode->i_private);
565 struct seq_file *sf = file->private_data;
566 struct mtk_phy_instance *inst = sf->private;
567 struct u3phy_banks *u3_banks = &inst->u3_banks;
568 void __iomem *phyd = u3_banks->phyd;
571 int ret = debugfs_get_aux_num(sf->file);
584 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,
619 debugfs_create_file_aux_num(u3_phy_files[i], 0644, inst->phy->debugfs,
625 struct mtk_phy_instance *inst = sf->private;
628 switch (inst->type) {
657 debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops);
659 switch (inst->type) {
682 struct u2phy_banks *u2_banks = &instance->u2_banks;
683 void __iomem *fmreg = u2_banks->fmreg;
684 void __iomem *com = u2_banks->com;
690 if (tphy->pdata->version == MTK_PHY_V3)
694 if (instance->eye_src)
708 if (tphy->pdata->version == MTK_PHY_V1)
709 tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);
730 tmp = tphy->src_ref_clk * tphy->src_coef;
737 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
738 instance->index, fm_out, calibration_val,
739 tphy->src_ref_clk, tphy->src_coef);
752 struct u3phy_banks *u3_banks = &instance->u3_banks;
753 void __iomem *phya = u3_banks->phya;
754 void __iomem *phyd = u3_banks->phyd;
756 if (instance->type_force_mode) {
761 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
763 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
767 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
769 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
774 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
784 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,
795 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
801 struct u2phy_banks *u2_banks = &instance->u2_banks;
802 void __iomem *com = u2_banks->com;
804 if (!tphy->pdata->sw_pll_48m_to_26m)
820 struct u2phy_banks *u2_banks = &instance->u2_banks;
821 void __iomem *com = u2_banks->com;
822 u32 index = instance->index;
839 if (tphy->pdata->avoid_rx_sen_degradation) {
860 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
866 struct u2phy_banks *u2_banks = &instance->u2_banks;
867 void __iomem *com = u2_banks->com;
868 u32 index = instance->index;
877 if (tphy->pdata->avoid_rx_sen_degradation && index) {
882 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
888 struct u2phy_banks *u2_banks = &instance->u2_banks;
889 void __iomem *com = u2_banks->com;
890 u32 index = instance->index;
899 if (tphy->pdata->avoid_rx_sen_degradation && index) {
905 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
911 struct u2phy_banks *u2_banks = &instance->u2_banks;
912 void __iomem *com = u2_banks->com;
913 u32 index = instance->index;
915 if (tphy->pdata->avoid_rx_sen_degradation && index) {
926 struct u2phy_banks *u2_banks = &instance->u2_banks;
929 tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
944 writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
950 struct u3phy_banks *u3_banks = &instance->u3_banks;
951 void __iomem *phya = u3_banks->phya;
953 if (tphy->pdata->version != MTK_PHY_V1)
966 /* SSC delta -5000ppm */
985 /* Tx Detect Rx Timing: 10us -> 5us */
986 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
989 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
994 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
1000 struct u3phy_banks *bank = &instance->u3_banks;
1002 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
1005 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
1013 struct u3phy_banks *bank = &instance->u3_banks;
1015 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
1018 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
1025 struct u3phy_banks *u3_banks = &instance->u3_banks;
1026 void __iomem *phyd = u3_banks->phyd;
1064 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
1070 struct u2phy_banks *u2_banks = &instance->u2_banks;
1071 struct u3phy_banks *u3_banks = &instance->u3_banks;
1073 switch (instance->type) {
1075 u2_banks->misc = NULL;
1076 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
1077 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
1081 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
1082 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
1083 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1084 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
1087 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1090 dev_err(tphy->dev, "incompatible PHY type\n");
1098 struct u2phy_banks *u2_banks = &instance->u2_banks;
1099 struct u3phy_banks *u3_banks = &instance->u3_banks;
1101 switch (instance->type) {
1103 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
1104 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
1105 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
1109 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
1110 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
1111 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
1112 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
1115 dev_err(tphy->dev, "incompatible PHY type\n");
1123 struct device *dev = &instance->phy->dev;
1125 if (instance->type == PHY_TYPE_USB3)
1126 instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");
1128 if (instance->type != PHY_TYPE_USB2)
1131 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
1132 device_property_read_u32(dev, "mediatek,eye-src",
1133 &instance->eye_src);
1134 device_property_read_u32(dev, "mediatek,eye-vrt",
1135 &instance->eye_vrt);
1136 device_property_read_u32(dev, "mediatek,eye-term",
1137 &instance->eye_term);
1139 &instance->intr);
1141 &instance->discth);
1142 device_property_read_u32(dev, "mediatek,pre-emphasis",
1143 &instance->pre_emphasis);
1144 dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
1145 instance->bc12_en, instance->eye_src,
1146 instance->eye_vrt, instance->eye_term,
1147 instance->intr, instance->discth);
1148 dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);
1154 struct u2phy_banks *u2_banks = &instance->u2_banks;
1155 void __iomem *com = u2_banks->com;
1157 if (instance->bc12_en) /* BC1.2 path Enable */
1160 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
1162 instance->eye_src);
1164 if (instance->eye_vrt)
1166 instance->eye_vrt);
1168 if (instance->eye_term)
1170 instance->eye_term);
1172 if (instance->intr) {
1173 if (u2_banks->misc)
1174 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,
1178 instance->intr);
1181 if (instance->discth)
1183 instance->discth);
1185 if (instance->pre_emphasis)
1187 instance->pre_emphasis);
1198 if (!of_property_read_bool(dn, "mediatek,syscon-type"))
1201 ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
1206 instance->type_sw_reg = args.args[0];
1207 instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
1208 instance->type_sw = syscon_node_to_regmap(args.np);
1210 dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
1211 instance->type_sw_reg, instance->type_sw_index);
1213 return PTR_ERR_OR_ZERO(instance->type_sw);
1221 if (!instance->type_sw)
1224 switch (instance->type) {
1242 offset = instance->type_sw_index * BITS_PER_BYTE;
1243 regmap_update_bits(instance->type_sw, instance->type_sw_reg,
1251 struct device *dev = &instance->phy->dev;
1255 if (!tphy->pdata->sw_efuse_supported) {
1256 instance->efuse_sw_en = 0;
1261 instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");
1262 if (!instance->efuse_sw_en)
1265 switch (instance->type) {
1267 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1274 if (!instance->efuse_intr) {
1276 instance->efuse_sw_en = 0;
1280 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
1285 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1291 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
1297 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
1304 if (!instance->efuse_intr &&
1305 !instance->efuse_rx_imp &&
1306 !instance->efuse_tx_imp) {
1308 instance->efuse_sw_en = 0;
1312 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
1313 instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
1316 dev_err(dev, "no sw efuse for type %d\n", instance->type);
1317 ret = -EINVAL;
1325 struct device *dev = &instance->phy->dev;
1326 struct u2phy_banks *u2_banks = &instance->u2_banks;
1327 struct u3phy_banks *u3_banks = &instance->u3_banks;
1329 if (!instance->efuse_sw_en)
1332 switch (instance->type) {
1334 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);
1336 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
1337 instance->efuse_intr);
1341 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);
1343 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
1344 instance->efuse_tx_imp);
1345 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
1347 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
1348 instance->efuse_rx_imp);
1349 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
1351 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,
1352 instance->efuse_intr);
1355 dev_warn(dev, "no sw efuse for type %d\n", instance->type);
1363 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1366 ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);
1372 switch (instance->type) {
1390 dev_err(tphy->dev, "incompatible PHY type\n");
1391 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1392 return -EINVAL;
1401 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1403 if (instance->type == PHY_TYPE_USB2) {
1406 } else if (instance->type == PHY_TYPE_PCIE) {
1416 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1418 if (instance->type == PHY_TYPE_USB2)
1420 else if (instance->type == PHY_TYPE_PCIE)
1429 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1431 if (instance->type == PHY_TYPE_USB2)
1434 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1441 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1443 if (instance->type == PHY_TYPE_USB2)
1454 struct device_node *phy_np = args->np;
1458 if (args->args_count != 1) {
1460 return ERR_PTR(-EINVAL);
1463 for (index = 0; index < tphy->nphys; index++)
1464 if (phy_np == tphy->phys[index]->phy->dev.of_node) {
1465 instance = tphy->phys[index];
1471 return ERR_PTR(-EINVAL);
1474 instance->type = args->args[0];
1475 if (!(instance->type == PHY_TYPE_USB2 ||
1476 instance->type == PHY_TYPE_USB3 ||
1477 instance->type == PHY_TYPE_PCIE ||
1478 instance->type == PHY_TYPE_SATA ||
1479 instance->type == PHY_TYPE_SGMII)) {
1480 dev_err(dev, "unsupported device type: %d\n", instance->type);
1481 return ERR_PTR(-EINVAL);
1484 switch (tphy->pdata->version) {
1494 return ERR_PTR(-EINVAL);
1505 return instance->phy;
1545 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1546 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1547 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1548 { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1549 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1550 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1551 { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1558 struct device *dev = &pdev->dev;
1559 struct device_node *np = dev->of_node;
1568 return -ENOMEM;
1570 tphy->pdata = of_device_get_match_data(dev);
1571 if (!tphy->pdata)
1572 return -EINVAL;
1574 tphy->nphys = of_get_child_count(np);
1575 tphy->phys = devm_kcalloc(dev, tphy->nphys,
1576 sizeof(*tphy->phys), GFP_KERNEL);
1577 if (!tphy->phys)
1578 return -ENOMEM;
1580 tphy->dev = dev;
1585 if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1587 tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1588 if (IS_ERR(tphy->sif_base)) {
1590 return PTR_ERR(tphy->sif_base);
1594 if (tphy->pdata->version < MTK_PHY_V3) {
1595 tphy->src_ref_clk = U3P_REF_CLK;
1596 tphy->src_coef = U3P_SLEW_RATE_COEF;
1598 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1599 &tphy->src_ref_clk);
1600 device_property_read_u32(dev, "mediatek,src-coef",
1601 &tphy->src_coef);
1614 return -ENOMEM;
1616 tphy->phys[port] = instance;
1624 subdev = &phy->dev;
1627 dev_err(subdev, "failed to get address resource(id-%d)\n",
1632 instance->port_base = devm_ioremap_resource(subdev, &res);
1633 if (IS_ERR(instance->port_base))
1634 return PTR_ERR(instance->port_base);
1636 instance->phy = phy;
1637 instance->index = port;
1641 clks = instance->clks;
1661 .name = "mtk-tphy",
1669 MODULE_DESCRIPTION("MediaTek T-PHY driver");