682 	struct mtk_phy_instance *instance)  in hs_slew_rate_calibrate()  argument
684 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in hs_slew_rate_calibrate()
698 	if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef)  in hs_slew_rate_calibrate()
713 		tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);  in hs_slew_rate_calibrate()
742 		instance->index, fm_out, calibration_val,  in hs_slew_rate_calibrate()
754 	struct mtk_phy_instance *instance)  in u3_phy_instance_init()  argument
756 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in u3_phy_instance_init()
760 	if (instance->type_force_mode) {  in u3_phy_instance_init()
799 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in u3_phy_instance_init()
803 	struct mtk_phy_instance *instance)  in u2_phy_pll_26m_set()  argument
805 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_pll_26m_set()
822 	struct mtk_phy_instance *instance)  in u2_phy_instance_init()  argument
824 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_init()
826 	u32 index = instance->index;  in u2_phy_instance_init()
862 	u2_phy_pll_26m_set(tphy, instance);  in u2_phy_instance_init()
868 	struct mtk_phy_instance *instance)  in u2_phy_instance_power_on()  argument
870 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_on()
872 	u32 index = instance->index;  in u2_phy_instance_power_on()
890 	struct mtk_phy_instance *instance)  in u2_phy_instance_power_off()  argument
892 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_off()
894 	u32 index = instance->index;  in u2_phy_instance_power_off()
913 	struct mtk_phy_instance *instance)  in u2_phy_instance_exit()  argument
915 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_exit()
917 	u32 index = instance->index;  in u2_phy_instance_exit()
927 				     struct mtk_phy_instance *instance,  in u2_phy_instance_set_mode()  argument
930 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_set_mode()
952 	struct mtk_phy_instance *instance)  in pcie_phy_instance_init()  argument
954 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in pcie_phy_instance_init()
998 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in pcie_phy_instance_init()
1002 	struct mtk_phy_instance *instance)  in pcie_phy_instance_power_on()  argument
1004 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_on()
1014 	struct mtk_phy_instance *instance)  in pcie_phy_instance_power_off()  argument
1017 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_off()
1027 	struct mtk_phy_instance *instance)  in sata_phy_instance_init()  argument
1029 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in sata_phy_instance_init()
1068 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in sata_phy_instance_init()
1072 			      struct mtk_phy_instance *instance)  in phy_v1_banks_init()  argument
1074 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v1_banks_init()
1075 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v1_banks_init()
1077 	switch (instance->type) {  in phy_v1_banks_init()
1081 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;  in phy_v1_banks_init()
1087 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1088 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
1091 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
1100 			      struct mtk_phy_instance *instance)  in phy_v2_banks_init()  argument
1102 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v2_banks_init()
1103 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v2_banks_init()
1105 	switch (instance->type) {  in phy_v2_banks_init()
1107 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;  in phy_v2_banks_init()
1108 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;  in phy_v2_banks_init()
1109 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;  in phy_v2_banks_init()
1113 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;  in phy_v2_banks_init()
1114 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;  in phy_v2_banks_init()
1115 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;  in phy_v2_banks_init()
1116 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
1125 				struct mtk_phy_instance *instance)  in phy_parse_property()  argument
1127 	struct device *dev = &instance->phy->dev;  in phy_parse_property()
1129 	if (instance->type == PHY_TYPE_USB3)  in phy_parse_property()
1130 		instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");  in phy_parse_property()
1132 	if (instance->type != PHY_TYPE_USB2)  in phy_parse_property()
1135 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");  in phy_parse_property()
1137 				 &instance->eye_src);  in phy_parse_property()
1139 				 &instance->eye_vrt);  in phy_parse_property()
1141 				 &instance->eye_term);  in phy_parse_property()
1143 				 &instance->intr);  in phy_parse_property()
1145 				 &instance->discth);  in phy_parse_property()
1147 				 &instance->pre_emphasis);  in phy_parse_property()
1149 		instance->bc12_en, instance->eye_src,  in phy_parse_property()
1150 		instance->eye_vrt, instance->eye_term,  in phy_parse_property()
1151 		instance->intr, instance->discth);  in phy_parse_property()
1152 	dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);  in phy_parse_property()
1156 			     struct mtk_phy_instance *instance)  in u2_phy_props_set()  argument
1158 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_props_set()
1161 	if (instance->bc12_en) /* BC1.2 path Enable */  in u2_phy_props_set()
1164 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)  in u2_phy_props_set()
1166 				     instance->eye_src);  in u2_phy_props_set()
1168 	if (instance->eye_vrt)  in u2_phy_props_set()
1170 				     instance->eye_vrt);  in u2_phy_props_set()
1172 	if (instance->eye_term)  in u2_phy_props_set()
1174 				     instance->eye_term);  in u2_phy_props_set()
1176 	if (instance->intr) {  in u2_phy_props_set()
1182 				     instance->intr);  in u2_phy_props_set()
1185 	if (instance->discth)  in u2_phy_props_set()
1187 				     instance->discth);  in u2_phy_props_set()
1189 	if (instance->pre_emphasis)  in u2_phy_props_set()
1191 				     instance->pre_emphasis);  in u2_phy_props_set()
1195 static int phy_type_syscon_get(struct mtk_phy_instance *instance,  in phy_type_syscon_get()  argument
1210 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
1211 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
1212 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
1214 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
1215 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
1217 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
1220 static int phy_type_set(struct mtk_phy_instance *instance)  in phy_type_set()  argument
1225 	if (!instance->type_sw)  in phy_type_set()
1228 	switch (instance->type) {  in phy_type_set()
1246 	offset = instance->type_sw_index * BITS_PER_BYTE;  in phy_type_set()
1247 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,  in phy_type_set()
1253 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)  in phy_efuse_get()  argument
1255 	struct device *dev = &instance->phy->dev;  in phy_efuse_get()
1260 		instance->efuse_sw_en = 0;  in phy_efuse_get()
1265 	instance->efuse_sw_en = device_property_present(dev, "nvmem-cells");  in phy_efuse_get()
1266 	if (!instance->efuse_sw_en)  in phy_efuse_get()
1269 	switch (instance->type) {  in phy_efuse_get()
1271 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1278 		if (!instance->efuse_intr) {  in phy_efuse_get()
1280 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1284 		dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);  in phy_efuse_get()
1289 		ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);  in phy_efuse_get()
1295 		ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);  in phy_efuse_get()
1301 		ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);  in phy_efuse_get()
1308 		if (!instance->efuse_intr &&  in phy_efuse_get()
1309 		    !instance->efuse_rx_imp &&  in phy_efuse_get()
1310 		    !instance->efuse_tx_imp) {  in phy_efuse_get()
1312 			instance->efuse_sw_en = 0;  in phy_efuse_get()
1317 			instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);  in phy_efuse_get()
1320 		dev_err(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_get()
1327 static void phy_efuse_set(struct mtk_phy_instance *instance)  in phy_efuse_set()  argument
1329 	struct device *dev = &instance->phy->dev;  in phy_efuse_set()
1330 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_efuse_set()
1331 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_efuse_set()
1333 	if (!instance->efuse_sw_en)  in phy_efuse_set()
1336 	switch (instance->type) {  in phy_efuse_set()
1341 				     instance->efuse_intr);  in phy_efuse_set()
1348 				    instance->efuse_tx_imp);  in phy_efuse_set()
1352 				    instance->efuse_rx_imp);  in phy_efuse_set()
1356 				    instance->efuse_intr);  in phy_efuse_set()
1359 		dev_warn(dev, "no sw efuse for type %d\n", instance->type);  in phy_efuse_set()
1366 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_init()  local
1370 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1374 	phy_efuse_set(instance);  in mtk_phy_init()
1376 	switch (instance->type) {  in mtk_phy_init()
1378 		u2_phy_instance_init(tphy, instance);  in mtk_phy_init()
1379 		u2_phy_props_set(tphy, instance);  in mtk_phy_init()
1382 		u3_phy_instance_init(tphy, instance);  in mtk_phy_init()
1385 		pcie_phy_instance_init(tphy, instance);  in mtk_phy_init()
1388 		sata_phy_instance_init(tphy, instance);  in mtk_phy_init()
1395 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1404 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_power_on()  local
1407 	if (instance->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
1408 		u2_phy_instance_power_on(tphy, instance);  in mtk_phy_power_on()
1409 		hs_slew_rate_calibrate(tphy, instance);  in mtk_phy_power_on()
1410 	} else if (instance->type == PHY_TYPE_PCIE) {  in mtk_phy_power_on()
1411 		pcie_phy_instance_power_on(tphy, instance);  in mtk_phy_power_on()
1419 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_power_off()  local
1422 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
1423 		u2_phy_instance_power_off(tphy, instance);  in mtk_phy_power_off()
1424 	else if (instance->type == PHY_TYPE_PCIE)  in mtk_phy_power_off()
1425 		pcie_phy_instance_power_off(tphy, instance);  in mtk_phy_power_off()
1432 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_exit()  local
1435 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_exit()
1436 		u2_phy_instance_exit(tphy, instance);  in mtk_phy_exit()
1438 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_exit()
1444 	struct mtk_phy_instance *instance = phy_get_drvdata(phy);  in mtk_phy_set_mode()  local
1447 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
1448 		u2_phy_instance_set_mode(tphy, instance, mode);  in mtk_phy_set_mode()
1457 	struct mtk_phy_instance *instance = NULL;  in mtk_phy_xlate()  local
1469 			instance = tphy->phys[index];  in mtk_phy_xlate()
1473 	if (!instance) {  in mtk_phy_xlate()
1478 	instance->type = args->args[0];  in mtk_phy_xlate()
1479 	if (!(instance->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
1480 	      instance->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
1481 	      instance->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
1482 	      instance->type == PHY_TYPE_SATA ||  in mtk_phy_xlate()
1483 	      instance->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
1484 		dev_err(dev, "unsupported device type: %d\n", instance->type);  in mtk_phy_xlate()
1490 		phy_v1_banks_init(tphy, instance);  in mtk_phy_xlate()
1494 		phy_v2_banks_init(tphy, instance);  in mtk_phy_xlate()
1501 	ret = phy_efuse_get(tphy, instance);  in mtk_phy_xlate()
1505 	phy_parse_property(tphy, instance);  in mtk_phy_xlate()
1506 	phy_type_set(instance);  in mtk_phy_xlate()
1507 	phy_debugfs_init(instance);  in mtk_phy_xlate()
1509 	return instance->phy;  in mtk_phy_xlate()
1615 		struct mtk_phy_instance *instance;  in mtk_tphy_probe()  local
1621 		instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);  in mtk_tphy_probe()
1622 		if (!instance)  in mtk_tphy_probe()
1625 		tphy->phys[port] = instance;  in mtk_tphy_probe()
1641 		instance->port_base = devm_ioremap_resource(subdev, &res);  in mtk_tphy_probe()
1642 		if (IS_ERR(instance->port_base))  in mtk_tphy_probe()
1643 			return PTR_ERR(instance->port_base);  in mtk_tphy_probe()
1645 		instance->phy = phy;  in mtk_tphy_probe()
1646 		instance->index = port;  in mtk_tphy_probe()
1647 		phy_set_drvdata(phy, instance);  in mtk_tphy_probe()
1650 		clks = instance->clks;  in mtk_tphy_probe()
1657 		retval = phy_type_syscon_get(instance, child_np);  in mtk_tphy_probe()