1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/nvmem-consumer.h>
16 #include "phy-mtk-io.h"
17 #include "phy-mtk-hdmi.h"
18 #include "phy-mtk-hdmi-mt8195.h"
23 	mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN);  in mtk_hdmi_ana_fifo_en()
29 	void __iomem *regs = hdmi_phy->regs;  in mtk_phy_tmds_clk_ratio()
45 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_sel_src()
57 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_perf()
90 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_set_hw()
130 		return -EINVAL;  in mtk_hdmi_pll_set_hw()
151 		return -EINVAL;  in mtk_hdmi_pll_set_hw()
174 		return -EINVAL;  in mtk_hdmi_pll_set_hw()
203 		mtk_phy_update_field(regs + HDMI_CTL_3, REG_HDMITXPLL_DIV, digital_div - 1);  in mtk_hdmi_pll_set_hw()
221 	if (tmds_clk < 25 * MEGA || tmds_clk > 594 * MEGA)  in mtk_hdmi_pll_calc()
222 		return -EINVAL;  in mtk_hdmi_pll_calc()
224 	if (tmds_clk >= 340 * MEGA)  in mtk_hdmi_pll_calc()
225 		hdmi_phy->tmds_over_340M = true;  in mtk_hdmi_pll_calc()
227 		hdmi_phy->tmds_over_340M = false;  in mtk_hdmi_pll_calc()
230 	da_hdmitx21_ref_ck = 26 * MEGA;  in mtk_hdmi_pll_calc()
238 	if (tmds_clk < 54 * MEGA)  in mtk_hdmi_pll_calc()
240 	else if (tmds_clk >= 54 * MEGA && (tmds_clk * 100) < 14835 * MEGA)  in mtk_hdmi_pll_calc()
242 	else if ((tmds_clk * 100) >= 14835 * MEGA && (tmds_clk * 10) < 2967 * MEGA)  in mtk_hdmi_pll_calc()
244 	else if ((tmds_clk * 10) >= 2967 * MEGA && tmds_clk <= 594 * MEGA)  in mtk_hdmi_pll_calc()
247 		return -EINVAL;  in mtk_hdmi_pll_calc()
259 	if (i == (ARRAY_SIZE(txpredivs) - 1) &&  in mtk_hdmi_pll_calc()
261 		return -EINVAL;  in mtk_hdmi_pll_calc()
264 		return -EINVAL;  in mtk_hdmi_pll_calc()
277 		return -EINVAL;  in mtk_hdmi_pll_calc()
284 	 * 24bit -> posdiv1 /10, 30bit -> posdiv1 /12.5,  in mtk_hdmi_pll_calc()
285 	 * 36bit -> posdiv1 /15, 48bit -> posdiv1 /10  in mtk_hdmi_pll_calc()
293 		return -EINVAL;  in mtk_hdmi_pll_calc()
303 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_drv_setting()
307 	u32 pixel_clk = hdmi_phy->pll_rate;  in mtk_hdmi_pll_drv_setting()
314 	 * pixel clk >= HD,  74.175MHZ <= pixel clk <= 300MHZ:  in mtk_hdmi_pll_drv_setting()
317 	 * 27M =< pixel clk < 74.175: disable impedance  in mtk_hdmi_pll_drv_setting()
322 	if (tmds_clk > 300 * MEGA && tmds_clk <= 594 * MEGA) {  in mtk_hdmi_pll_drv_setting()
327 	} else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) {  in mtk_hdmi_pll_drv_setting()
332 	} else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) {  in mtk_hdmi_pll_drv_setting()
338 		return -EINVAL;  in mtk_hdmi_pll_drv_setting()
360 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_prepare()
394 	void __iomem *regs = hdmi_phy->regs;  in mtk_hdmi_pll_unprepare()
413 	dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__, rate,  in mtk_hdmi_pll_set_rate()
424 	hdmi_phy->pll_rate = rate;  in mtk_hdmi_pll_round_rate()
433 	return hdmi_phy->pll_rate;  in mtk_hdmi_pll_recalc_rate()
446 	void __iomem *regs = hdmi_phy->regs;  in vtx_signal_en()
467 	struct phy_configure_opts_dp *dp_opts = &opts->dp;  in mtk_hdmi_phy_configure()
471 	ret = clk_set_rate(hdmi_phy->pll, dp_opts->link_rate);  in mtk_hdmi_phy_configure()
476 	mtk_phy_tmds_clk_ratio(hdmi_phy, hdmi_phy->tmds_over_340M);  in mtk_hdmi_phy_configure()