Lines Matching +full:32 +full:ma
272 * RG_HDMITXPLL_FBKDIV[32:0]:
273 * [32,24] 9bit integer, [23,0]:24bit fraction
278 if (pcw > GENMASK_ULL(32, 0))
281 fbkdiv_high = FIELD_GET(GENMASK_ULL(63, 32), pcw);
292 /* Digital clk divider, max /32 */
294 if (!(digital_div <= 32 && digital_div >= 1))
315 * data channel bias 24mA, clock channel bias 20mA
318 * data channel 20mA, clock channel 16mA
320 * data channel & clock channel bias 10mA
325 data_channel_bias = 0x3c; /* 24mA */
326 clk_channel_bias = 0x34; /* 20mA */
330 data_channel_bias = 0x34; /* 20mA */
331 clk_channel_bias = 0x2c; /* 16mA */
335 data_channel_bias = 0x14; /* 10mA */
336 clk_channel_bias = 0x14; /* 10mA */