Lines Matching refs:HDMI_CON2
23 #define HDMI_CON2 0x08 macro
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_prepare()
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_prepare()
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_prepare()
80 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_unprepare()
83 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_unprepare()
86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_unprepare()
115 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); in mtk_hdmi_pll_set_rate()
118 mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div); in mtk_hdmi_pll_set_rate()
159 tmp = readl(hdmi_phy->regs + HDMI_CON2); in mtk_hdmi_pll_recalc_rate()
184 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_phy_enable_tmds()
187 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_phy_enable_tmds()
190 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_phy_enable_tmds()
204 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_phy_disable_tmds()
207 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_phy_disable_tmds()
210 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_phy_disable_tmds()