Lines Matching defs:n
21 #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000)
23 #define MVEBU_COMPHY_SERDES_CFG0_GEN_RX(n) ((n) << 3)
24 #define MVEBU_COMPHY_SERDES_CFG0_GEN_TX(n) ((n) << 7)
29 #define MVEBU_COMPHY_SERDES_CFG1(n) (0x4 + (n) * 0x1000)
34 #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000)
36 #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000)
40 #define MVEBU_COMPHY_PWRPLL_CTRL(n) (0x804 + (n) * 0x1000)
41 #define MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(n) ((n) << 0)
42 #define MVEBU_COMPHY_PWRPLL_PHY_MODE(n) ((n) << 5)
43 #define MVEBU_COMPHY_IMP_CAL(n) (0x80c + (n) * 0x1000)
44 #define MVEBU_COMPHY_IMP_CAL_TX_EXT(n) ((n) << 10)
46 #define MVEBU_COMPHY_DFE_RES(n) (0x81c + (n) * 0x1000)
48 #define MVEBU_COMPHY_COEF(n) (0x828 + (n) * 0x1000)
51 #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000)
52 #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1)
53 #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7)
54 #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000)
55 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0)
56 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3)
57 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(n) ((n) << 6)
58 #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8)
60 #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11)
61 #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000)
62 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0)
64 #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000)
65 #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1)
66 #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000)
68 #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000)
69 #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5)
70 #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000)
73 #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000)
76 #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000)
78 #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000)
79 #define MVEBU_SP_CALIB_SAMPLER(n) ((n) << 8)
81 #define MVEBU_COMPHY_TX_SLEW_RATE(n) (0x974 + (n) * 0x1000)
82 #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5)
83 #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10)
84 #define MVEBU_COMPHY_DTL_CTRL(n) (0x984 + (n) * 0x1000)
86 #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000)
87 #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7)
88 #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000)
90 #define MVEBU_COMPHY_DME(n) (0xa28 + (n) * 0x1000)
92 #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000)
94 #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000)
95 #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0)
96 #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000)
99 #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000)
101 #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000)
102 #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8)
103 #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000)
104 #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0)
105 #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000)
106 #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0)
109 #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28)
112 #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28)
115 #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4)
117 #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4)
298 int i, n = ARRAY_SIZE(mvebu_comphy_cp110_modes);
307 for (i = 0; i < n; i++) {
316 if (i == n)
379 "unsupported comphy submode (%d) on lane %d\n",
401 "RXAUI is not supported on comphy lane %d\n",
784 dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
789 dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
794 dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
799 dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",
804 dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
809 dev_err(priv->dev, "unsupported Ethernet mode (%d)\n",
817 dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
821 dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
825 dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
831 dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
842 "unsupported SMC call, try updating your firmware\n");
845 "Firmware could not configure PHY %d with mode %d (ret: %d), trying legacy method\n",
1027 dev_warn(&pdev->dev, "cannot initialize clocks\n");
1043 dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
1049 dev_err(&pdev->dev, "invalid 'reg' property\n");