Lines Matching +full:7 +full:gbps
61 #define COMPHY_MODE_MASK GENMASK(7, 5)
69 #define SPEED_PLL_MASK GENMASK(7, 2)
93 #define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7)
112 #define CLK500M_EN BIT(7)
145 #define SPREAD_SPECTRUM_CLK_EN BIT(7)
163 #define PLL_READY_DLY_MASK GENMASK(7, 5)
170 #define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0)
300 /* 0 1 2 3 4 5 6 7 */
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
686 /* 7. Program COMPHY register PHY_MODE */ in mvebu_a3700_comphy_ethernet_power_on()
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or in mvebu_a3700_comphy_ethernet_power_on()
716 * PCIe speed 2.5/5 Gbps in mvebu_a3700_comphy_ethernet_power_on()
888 * 7. Unset G3 Spread Spectrum Clock Amplitude in mvebu_a3700_comphy_usb3_power_on()
956 * 14. Set max speed generation to USB3.0 5Gbps in mvebu_a3700_comphy_usb3_power_on()
1024 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in in mvebu_a3700_comphy_pcie_power_on()