Lines Matching +full:10 +full:base
42 #define DATA_BIT_WIDTH_10 (0x0 << 10)
43 #define DATA_BIT_WIDTH_20 (0x1 << 10)
44 #define DATA_BIT_WIDTH_40 (0x2 << 10)
47 #define PHY_GEN_MAX_1_5 (0x0 << 10)
48 #define PHY_GEN_MAX_3_0 (0x1 << 10)
49 #define PHY_GEN_MAX_6_0 (0x2 << 10)
58 void __iomem *base; member
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on()
93 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_on()
94 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
96 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
99 writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_on()
100 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
102 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
145 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_off()
146 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_off()
148 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_off()
207 priv->base = devm_ioremap(dev, res->start, resource_size(res)); in phy_berlin_sata_probe()
208 if (!priv->base) in phy_berlin_sata_probe()