1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
48 	struct clk *emmcclk;
64 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,  in intel_emmc_phy_power()
67 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);  in intel_emmc_phy_power()
75 	rate = clk_get_rate(priv->emmcclk);  in intel_emmc_phy_power()
78 		dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);  in intel_emmc_phy_power()
88 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,  in intel_emmc_phy_power()
91 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);  in intel_emmc_phy_power()
102 	ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG,  in intel_emmc_phy_power()
106 		dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);  in intel_emmc_phy_power()
111 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK,  in intel_emmc_phy_power()
114 		dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);  in intel_emmc_phy_power()
119 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK,  in intel_emmc_phy_power()
122 		dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);  in intel_emmc_phy_power()
140 	ret = regmap_read_poll_timeout(priv->syscfg,  in intel_emmc_phy_power()
145 		dev_err(&phy->dev, "dllrdy failed. ret=%d\n", ret);  in intel_emmc_phy_power()
159 	 * - PHY driver to probe  in intel_emmc_phy_init()
160 	 * - SDHCI driver to start probe  in intel_emmc_phy_init()
161 	 * - SDHCI driver to register it's clock  in intel_emmc_phy_init()
162 	 * - SDHCI driver to get the PHY  in intel_emmc_phy_init()
163 	 * - SDHCI driver to init the PHY  in intel_emmc_phy_init()
169 	priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");  in intel_emmc_phy_init()
170 	if (IS_ERR(priv->emmcclk)) {  in intel_emmc_phy_init()
171 		dev_err(&phy->dev, "ERROR: getting emmcclk\n");  in intel_emmc_phy_init()
172 		return PTR_ERR(priv->emmcclk);  in intel_emmc_phy_init()
182 	clk_put(priv->emmcclk);  in intel_emmc_phy_exit()
193 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK,  in intel_emmc_phy_power_on()
196 		dev_err(&phy->dev, "ERROR set drive-impednce-50ohm: %d\n", ret);  in intel_emmc_phy_power_on()
201 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA,  in intel_emmc_phy_power_on()
204 		dev_err(&phy->dev, "ERROR Set output tap delay : %d\n", ret);  in intel_emmc_phy_power_on()
209 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG,  in intel_emmc_phy_power_on()
212 		dev_err(&phy->dev, "ERROR: output tap dly select: %d\n", ret);  in intel_emmc_phy_power_on()
236 	struct device *dev = &pdev->dev;  in intel_emmc_phy_probe()
237 	struct device_node *np = dev->of_node;  in intel_emmc_phy_probe()
244 		return -ENOMEM;  in intel_emmc_phy_probe()
247 	priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon");  in intel_emmc_phy_probe()
248 	if (IS_ERR(priv->syscfg)) {  in intel_emmc_phy_probe()
250 		return PTR_ERR(priv->syscfg);  in intel_emmc_phy_probe()
266 	{ .compatible = "intel,lgm-emmc-phy" },
275 		.name	= "intel-emmc-phy",