1 // SPDX-License-Identifier: GPL-2.0
3  * Intel Combo-PHY driver
5  * Copyright (C) 2019-2020 Intel Corporation.
9 #include <linux/clk.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x)		((x)->parent->id)
38 #define PHY_ID(x)		((x)->id)
88 	struct clk		*core_clk;
107 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_iphy_enable()
108 	u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id);  in intel_cbphy_iphy_enable()
114 	return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid),  in intel_cbphy_iphy_enable()
120 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_pcie_refclk_cfg()
121 	u32 mask = BIT(cbphy->id * 2 + iphy->id);  in intel_cbphy_pcie_refclk_cfg()
127 	return regmap_update_bits(cbphy->syscfg, PAD_DIS_CFG, mask, val);  in intel_cbphy_pcie_refclk_cfg()
144 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_iphy_cfg()
151 	if (cbphy->aggr_mode != PHY_DL_MODE)  in intel_cbphy_iphy_cfg()
154 	return phy_cfg(&cbphy->iphy[PHY_1]);  in intel_cbphy_iphy_cfg()
159 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_pcie_en_pad_refclk()
164 		dev_err(cbphy->dev, "Failed to enable PCIe pad refclk\n");  in intel_cbphy_pcie_en_pad_refclk()
168 	if (cbphy->init_cnt)  in intel_cbphy_pcie_en_pad_refclk()
171 	combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,  in intel_cbphy_pcie_en_pad_refclk()
182 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_pcie_dis_pad_refclk()
187 		dev_err(cbphy->dev, "Failed to disable PCIe pad refclk\n");  in intel_cbphy_pcie_dis_pad_refclk()
191 	if (cbphy->init_cnt)  in intel_cbphy_pcie_dis_pad_refclk()
194 	combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,  in intel_cbphy_pcie_dis_pad_refclk()
203 	enum aggregated_mode aggr = cbphy->aggr_mode;  in intel_cbphy_set_mode()
204 	struct device *dev = cbphy->dev;  in intel_cbphy_set_mode()
208 	mode = cbphy->phy_mode;  in intel_cbphy_set_mode()
222 			return -EINVAL;  in intel_cbphy_set_mode()
228 		return -EINVAL;  in intel_cbphy_set_mode()
231 	ret = regmap_write(cbphy->hsiocfg, REG_COMBO_MODE(cbphy->bid), cb_mode);  in intel_cbphy_set_mode()
240 	reset_control_assert(cbphy->core_rst);  in intel_cbphy_rst_assert()
241 	reset_control_assert(cbphy->phy_rst);  in intel_cbphy_rst_assert()
246 	reset_control_deassert(cbphy->core_rst);  in intel_cbphy_rst_deassert()
247 	reset_control_deassert(cbphy->phy_rst);  in intel_cbphy_rst_deassert()
254 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_iphy_power_on()
257 	if (!cbphy->init_cnt) {  in intel_cbphy_iphy_power_on()
258 		ret = clk_prepare_enable(cbphy->core_clk);  in intel_cbphy_iphy_power_on()
260 			dev_err(cbphy->dev, "Clock enable failed!\n");  in intel_cbphy_iphy_power_on()
264 		ret = clk_set_rate(cbphy->core_clk, cbphy->clk_rate);  in intel_cbphy_iphy_power_on()
266 			dev_err(cbphy->dev, "Clock freq set to %lu failed!\n",  in intel_cbphy_iphy_power_on()
267 				cbphy->clk_rate);  in intel_cbphy_iphy_power_on()
280 		dev_err(cbphy->dev, "Failed enabling PHY core\n");  in intel_cbphy_iphy_power_on()
284 	ret = reset_control_deassert(iphy->app_rst);  in intel_cbphy_iphy_power_on()
286 		dev_err(cbphy->dev, "PHY(%u:%u) reset deassert failed!\n",  in intel_cbphy_iphy_power_on()
297 	clk_disable_unprepare(cbphy->core_clk);  in intel_cbphy_iphy_power_on()
304 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_iphy_power_off()
307 	ret = reset_control_assert(iphy->app_rst);  in intel_cbphy_iphy_power_off()
309 		dev_err(cbphy->dev, "PHY(%u:%u) reset assert failed!\n",  in intel_cbphy_iphy_power_off()
316 		dev_err(cbphy->dev, "Failed disabling PHY core\n");  in intel_cbphy_iphy_power_off()
320 	if (cbphy->init_cnt)  in intel_cbphy_iphy_power_off()
323 	clk_disable_unprepare(cbphy->core_clk);  in intel_cbphy_iphy_power_off()
332 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_init()
335 	mutex_lock(&cbphy->lock);  in intel_cbphy_init()
340 	if (cbphy->phy_mode == PHY_PCIE_MODE) {  in intel_cbphy_init()
346 	cbphy->init_cnt++;  in intel_cbphy_init()
349 	mutex_unlock(&cbphy->lock);  in intel_cbphy_init()
357 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_exit()
360 	mutex_lock(&cbphy->lock);  in intel_cbphy_exit()
361 	cbphy->init_cnt--;  in intel_cbphy_exit()
362 	if (cbphy->phy_mode == PHY_PCIE_MODE) {  in intel_cbphy_exit()
371 	mutex_unlock(&cbphy->lock);  in intel_cbphy_exit()
379 	struct intel_combo_phy *cbphy = iphy->parent;  in intel_cbphy_calibrate()
380 	void __iomem *cr_base = cbphy->cr_base;  in intel_cbphy_calibrate()
383 	if (cbphy->phy_mode != PHY_XPCS_MODE)  in intel_cbphy_calibrate()
395 		dev_err(cbphy->dev, "RX Adaptation failed!\n");  in intel_cbphy_calibrate()
397 		dev_dbg(cbphy->dev, "RX Adaptation success!\n");  in intel_cbphy_calibrate()
408 	struct device *dev = cbphy->dev;  in intel_cbphy_fwnode_parse()
415 	cbphy->core_clk = devm_clk_get(dev, NULL);  in intel_cbphy_fwnode_parse()
416 	if (IS_ERR(cbphy->core_clk))  in intel_cbphy_fwnode_parse()
417 		return dev_err_probe(dev, PTR_ERR(cbphy->core_clk),  in intel_cbphy_fwnode_parse()
418 				     "Get clk failed!\n");  in intel_cbphy_fwnode_parse()
420 	cbphy->core_rst = devm_reset_control_get_optional(dev, "core");  in intel_cbphy_fwnode_parse()
421 	if (IS_ERR(cbphy->core_rst))  in intel_cbphy_fwnode_parse()
422 		return dev_err_probe(dev, PTR_ERR(cbphy->core_rst),  in intel_cbphy_fwnode_parse()
425 	cbphy->phy_rst = devm_reset_control_get_optional(dev, "phy");  in intel_cbphy_fwnode_parse()
426 	if (IS_ERR(cbphy->phy_rst))  in intel_cbphy_fwnode_parse()
427 		return dev_err_probe(dev, PTR_ERR(cbphy->phy_rst),  in intel_cbphy_fwnode_parse()
430 	cbphy->iphy[0].app_rst = devm_reset_control_get_optional(dev, "iphy0");  in intel_cbphy_fwnode_parse()
431 	if (IS_ERR(cbphy->iphy[0].app_rst))  in intel_cbphy_fwnode_parse()
432 		return dev_err_probe(dev, PTR_ERR(cbphy->iphy[0].app_rst),  in intel_cbphy_fwnode_parse()
435 	cbphy->iphy[1].app_rst = devm_reset_control_get_optional(dev, "iphy1");  in intel_cbphy_fwnode_parse()
436 	if (IS_ERR(cbphy->iphy[1].app_rst))  in intel_cbphy_fwnode_parse()
437 		return dev_err_probe(dev, PTR_ERR(cbphy->iphy[1].app_rst),  in intel_cbphy_fwnode_parse()
440 	cbphy->app_base = devm_platform_ioremap_resource_byname(pdev, "app");  in intel_cbphy_fwnode_parse()
441 	if (IS_ERR(cbphy->app_base))  in intel_cbphy_fwnode_parse()
442 		return PTR_ERR(cbphy->app_base);  in intel_cbphy_fwnode_parse()
444 	cbphy->cr_base = devm_platform_ioremap_resource_byname(pdev, "core");  in intel_cbphy_fwnode_parse()
445 	if (IS_ERR(cbphy->cr_base))  in intel_cbphy_fwnode_parse()
446 		return PTR_ERR(cbphy->cr_base);  in intel_cbphy_fwnode_parse()
458 	cbphy->id = ref.args[0];  in intel_cbphy_fwnode_parse()
459 	cbphy->syscfg = device_node_to_regmap(to_of_node(ref.fwnode));  in intel_cbphy_fwnode_parse()
467 	cbphy->bid = ref.args[0];  in intel_cbphy_fwnode_parse()
468 	cbphy->hsiocfg = device_node_to_regmap(to_of_node(ref.fwnode));  in intel_cbphy_fwnode_parse()
471 	ret = fwnode_property_read_u32_array(fwnode, "intel,phy-mode", &val, 1);  in intel_cbphy_fwnode_parse()
477 		cbphy->phy_mode = PHY_PCIE_MODE;  in intel_cbphy_fwnode_parse()
481 		cbphy->phy_mode = PHY_SATA_MODE;  in intel_cbphy_fwnode_parse()
485 		cbphy->phy_mode = PHY_XPCS_MODE;  in intel_cbphy_fwnode_parse()
490 		return -EINVAL;  in intel_cbphy_fwnode_parse()
493 	cbphy->clk_rate = intel_iphy_clk_rates[cbphy->phy_mode];  in intel_cbphy_fwnode_parse()
496 		cbphy->aggr_mode = PHY_DL_MODE;  in intel_cbphy_fwnode_parse()
498 		cbphy->aggr_mode = PHY_SL_MODE;  in intel_cbphy_fwnode_parse()
516 	if (args->args_count < 1) {  in intel_cbphy_xlate()
518 		return ERR_PTR(-EINVAL);  in intel_cbphy_xlate()
521 	iphy_id = args->args[0];  in intel_cbphy_xlate()
524 		return ERR_PTR(-EINVAL);  in intel_cbphy_xlate()
527 	if (cbphy->aggr_mode == PHY_DL_MODE && iphy_id == PHY_1) {  in intel_cbphy_xlate()
529 		return ERR_PTR(-EINVAL);  in intel_cbphy_xlate()
532 	return cbphy->iphy[iphy_id].phy;  in intel_cbphy_xlate()
538 	struct device *dev = cbphy->dev;  in intel_cbphy_create()
543 		iphy = &cbphy->iphy[i];  in intel_cbphy_create()
544 		iphy->parent = cbphy;  in intel_cbphy_create()
545 		iphy->id = i;  in intel_cbphy_create()
548 		if (cbphy->aggr_mode == PHY_DL_MODE && iphy->id == PHY_1)  in intel_cbphy_create()
551 		iphy->phy = devm_phy_create(dev, NULL, &intel_cbphy_ops);  in intel_cbphy_create()
552 		if (IS_ERR(iphy->phy)) {  in intel_cbphy_create()
556 			return PTR_ERR(iphy->phy);  in intel_cbphy_create()
559 		phy_set_drvdata(iphy->phy, iphy);  in intel_cbphy_create()
572 	struct device *dev = &pdev->dev;  in intel_cbphy_probe()
578 		return -ENOMEM;  in intel_cbphy_probe()
580 	cbphy->dev = dev;  in intel_cbphy_probe()
581 	cbphy->init_cnt = 0;  in intel_cbphy_probe()
582 	mutex_init(&cbphy->lock);  in intel_cbphy_probe()
597 	clk_disable_unprepare(cbphy->core_clk);  in intel_cbphy_remove()
601 	{ .compatible = "intel,combo-phy" },
602 	{ .compatible = "intel,combophy-lgm" },
610 		.name = "intel-combo-phy",
617 MODULE_DESCRIPTION("Intel Combo-phy driver");