1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/delay.h>
66 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,  in keembay_emmc_phy_power()
69 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);  in keembay_emmc_phy_power()
73 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,  in keembay_emmc_phy_power()
76 		dev_err(&phy->dev, "turn off the dll failed: %d\n", ret);  in keembay_emmc_phy_power()
84 	mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000);  in keembay_emmc_phy_power()
100 		dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);  in keembay_emmc_phy_power()
105 	 * value, so we may need a little margin here  in keembay_emmc_phy_power()
109 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,  in keembay_emmc_phy_power()
112 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);  in keembay_emmc_phy_power()
120 	 * failure cases are found which indicates we should be more tolerant  in keembay_emmc_phy_power()
123 	ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,  in keembay_emmc_phy_power()
127 		dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);  in keembay_emmc_phy_power()
132 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_2, SEL_FREQ_MASK,  in keembay_emmc_phy_power()
135 		dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);  in keembay_emmc_phy_power()
140 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,  in keembay_emmc_phy_power()
143 		dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);  in keembay_emmc_phy_power()
148 	 * We turned on the DLL even though the rate was 0 because we the  in keembay_emmc_phy_power()
149 	 * clock might be turned on later.  ...but we can't wait for the DLL  in keembay_emmc_phy_power()
153 	 * Technically we should be checking the lock later when the clock  in keembay_emmc_phy_power()
154 	 * is turned on, but for now we won't.  in keembay_emmc_phy_power()
160 	 * After enabling analog DLL circuits docs say that we need 10.2 us if  in keembay_emmc_phy_power()
162 	 * with clock speed. If we are powering on the PHY and the card clock  in keembay_emmc_phy_power()
165 	 * hopefully we won't be running at 100 kHz, but we should still make  in keembay_emmc_phy_power()
166 	 * sure we wait long enough.  in keembay_emmc_phy_power()
169 	 * extra long to lock for reasons that aren't understood. In some  in keembay_emmc_phy_power()
170 	 * extreme cases we've seen it take up to over 10ms (!). We'll be  in keembay_emmc_phy_power()
173 	ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,  in keembay_emmc_phy_power()
177 		dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);  in keembay_emmc_phy_power()
187 	 * We purposely get the clock here and not in probe to avoid the  in keembay_emmc_phy_init()
188 	 * circular dependency problem. We expect:  in keembay_emmc_phy_init()
189 	 * - PHY driver to probe  in keembay_emmc_phy_init()
190 	 * - SDHCI driver to start probe  in keembay_emmc_phy_init()
191 	 * - SDHCI driver to register it's clock  in keembay_emmc_phy_init()
192 	 * - SDHCI driver to get the PHY  in keembay_emmc_phy_init()
193 	 * - SDHCI driver to init the PHY  in keembay_emmc_phy_init()
198 	priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");  in keembay_emmc_phy_init()
200 	return PTR_ERR_OR_ZERO(priv->emmcclk);  in keembay_emmc_phy_init()
207 	clk_put(priv->emmcclk);  in keembay_emmc_phy_exit()
217 	/* Delay chain based txclk: enable */  in keembay_emmc_phy_power_on()
218 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, SEL_DLY_TXCLK_MASK,  in keembay_emmc_phy_power_on()
221 		dev_err(&phy->dev, "ERROR: delay chain txclk set: %d\n", ret);  in keembay_emmc_phy_power_on()
225 	/* Output tap delay: enable */  in keembay_emmc_phy_power_on()
226 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_ENA_MASK,  in keembay_emmc_phy_power_on()
229 		dev_err(&phy->dev, "ERROR: output tap delay set: %d\n", ret);  in keembay_emmc_phy_power_on()
233 	/* Output tap delay */  in keembay_emmc_phy_power_on()
234 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_SEL_MASK,  in keembay_emmc_phy_power_on()
237 		dev_err(&phy->dev, "ERROR: output tap delay select: %d\n", ret);  in keembay_emmc_phy_power_on()
261 	struct device *dev = &pdev->dev;  in keembay_emmc_phy_probe()
262 	struct device_node *np = dev->of_node;  in keembay_emmc_phy_probe()
270 		return -ENOMEM;  in keembay_emmc_phy_probe()
276 	priv->syscfg = devm_regmap_init_mmio(dev, base, &keembay_regmap_config);  in keembay_emmc_phy_probe()
277 	if (IS_ERR(priv->syscfg))  in keembay_emmc_phy_probe()
278 		return PTR_ERR(priv->syscfg);  in keembay_emmc_phy_probe()
292 	{ .compatible = "intel,keembay-emmc-phy" },
300 		.name	= "keembay-emmc-phy",