Lines Matching +full:hi970 +full:- +full:pcie +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe phy driver for Kirin 970
29 #include <linux/phy/phy.h>
37 /* PCIe CTRL registers */
49 /* PCIe PHY registers */
173 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
176 writel(val, phy->base + APB_PHY_START_ADDR + reg);
179 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
181 return readl(phy->base + APB_PHY_START_ADDR + reg);
184 static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
189 regval = hi3670_apb_phy_readl(phy, reg);
192 hi3670_apb_phy_writel(phy, regval, reg);
195 static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
198 writel(val, phy->base + reg);
201 static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
204 return readl(phy->base + reg);
207 static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
211 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
217 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
220 static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
222 struct device *dev = phy->dev;
226 np = dev->of_node;
228 ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
229 phy->eye_param, NUM_EYEPARAM);
235 phy->eye_param[i] = EYEPARAM_NOCFG;
238 static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
242 val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
244 if (phy->eye_param[1] != EYEPARAM_NOCFG) {
246 val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
249 kirin_apb_natural_phy_writel(phy, val,
252 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
254 if (phy->eye_param[2] != EYEPARAM_NOCFG) {
255 val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
259 if (phy->eye_param[3] != EYEPARAM_NOCFG) {
260 val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
264 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
266 val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
267 if (phy->eye_param[0] != EYEPARAM_NOCFG) {
269 val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
272 kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
274 val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
275 if (phy->eye_param[4] != EYEPARAM_NOCFG) {
277 val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
280 kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
283 static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)
288 regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,
291 regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
293 regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
296 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
299 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
302 hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,
307 hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,
311 static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)
313 hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,
316 hi3670_apb_phy_updatel(phy,
321 hi3670_apb_phy_updatel(phy,
325 hi3670_apb_phy_updatel(phy,
335 hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,
339 static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
341 struct device *dev = phy->dev;
347 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
351 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
355 return -EINVAL;
357 time--;
359 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
362 hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
366 hi3670_apb_phy_updatel(phy,
371 hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
379 static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)
383 regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,
387 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
391 static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)
395 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
402 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
405 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);
408 static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)
412 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
431 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
434 static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)
439 regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,
442 hi3670_pcie_oe_ctrl(phy, true);
445 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
447 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
450 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
455 regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
457 regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
460 regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
463 hi3670_pcie_oe_ctrl(phy, false);
467 static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)
469 struct device *dev = phy->dev;
476 hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,
479 hi3670_pcie_pll_init(phy);
481 ret = hi3670_pcie_pll_ctrl(phy, true);
484 return -EINVAL;
486 hi3670_pcie_hp_debounce_gt(phy, true);
487 hi3670_pcie_phyref_gt(phy, true);
488 hi3670_pcie_ioref_gt(phy, true);
490 ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);
499 hi3670_pcie_ioref_gt(phy, false);
500 hi3670_pcie_phyref_gt(phy, false);
501 hi3670_pcie_hp_debounce_gt(phy, false);
503 hi3670_pcie_pll_ctrl(phy, false);
508 static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)
510 struct device *dev = phy->dev;
515 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
522 time--;
523 val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
529 static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
531 struct device *dev = phy->dev;
542 regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
545 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
549 dev_err(dev, "Failed to reverse noc power-status\n");
550 return -EINVAL;
552 time--;
553 regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
559 static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
562 struct device *dev = phy->dev;
565 pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");
567 dev_err(dev, "no pcie node found in %s\n",
568 dev->parent->of_node->full_name);
569 return -ENODEV;
574 dev_err(dev, "Didn't find pcie device\n");
575 return -ENODEV;
580 * pcie-kirin currently registers directly just one regmap (although
586 phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");
587 if (!phy->apb) {
589 return -ENODEV;
595 static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)
602 ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
606 ret = clk_prepare_enable(phy->phy_ref_clk);
610 ret = clk_prepare_enable(phy->apb_sys_clk);
614 ret = clk_prepare_enable(phy->apb_phy_clk);
618 ret = clk_prepare_enable(phy->aclk);
622 ret = clk_prepare_enable(phy->aux_clk);
629 clk_disable_unprepare(phy->aux_clk);
631 clk_disable_unprepare(phy->aclk);
633 clk_disable_unprepare(phy->apb_phy_clk);
635 clk_disable_unprepare(phy->apb_sys_clk);
637 clk_disable_unprepare(phy->phy_ref_clk);
642 static int hi3670_pcie_phy_init(struct phy *generic_phy)
644 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
649 * access the reset-gpios and the APB registers, both from the
650 * pcie-kirin driver.
652 * The APB is obtained via the pcie driver's regmap
653 * Such kind of resource can only be obtained during the PCIe
654 * power_on sequence, as the code inside pcie-kirin needs to
658 ret = hi3670_pcie_get_resources_from_pcie(phy);
665 static int hi3670_pcie_phy_power_on(struct phy *generic_phy)
667 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
671 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
674 hi3670_pcie_phy_oe_enable(phy, true);
676 ret = kirin_pcie_clk_ctrl(phy, true);
680 /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
681 regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
682 regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,
684 regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,
687 hi3670_pcie_natural_cfg(phy);
689 ret = hi3670_pcie_allclk_ctrl(phy, true);
694 hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,
698 regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
700 regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
703 ret = is_pipe_clk_stable(phy);
707 hi3670_pcie_set_eyeparam(phy);
709 ret = hi3670_pcie_noc_power(phy, false);
716 kirin_pcie_clk_ctrl(phy, false);
720 static int hi3670_pcie_phy_power_off(struct phy *generic_phy)
722 struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
724 hi3670_pcie_phy_oe_enable(phy, false);
726 hi3670_pcie_allclk_ctrl(phy, false);
729 regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);
733 * kirin_pcie_clk_ctrl(phy, false);
735 * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off
737 * While clk-hi3670 is not fixed, we cannot risk disabling clocks here.
750 static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
753 struct device *dev = &pdev->dev;
756 phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");
757 if (IS_ERR(phy->crgctrl))
758 return PTR_ERR(phy->crgctrl);
760 phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");
761 if (IS_ERR(phy->sysctrl))
762 return PTR_ERR(phy->sysctrl);
764 phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
765 if (IS_ERR(phy->pmctrl))
766 return PTR_ERR(phy->pmctrl);
769 phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
770 if (IS_ERR(phy->phy_ref_clk))
771 return PTR_ERR(phy->phy_ref_clk);
773 phy->aux_clk = devm_clk_get(dev, "aux");
774 if (IS_ERR(phy->aux_clk))
775 return PTR_ERR(phy->aux_clk);
777 phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");
778 if (IS_ERR(phy->apb_phy_clk))
779 return PTR_ERR(phy->apb_phy_clk);
781 phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");
782 if (IS_ERR(phy->apb_sys_clk))
783 return PTR_ERR(phy->apb_sys_clk);
785 phy->aclk = devm_clk_get(dev, "aclk");
786 if (IS_ERR(phy->aclk))
787 return PTR_ERR(phy->aclk);
790 phy->base = devm_platform_ioremap_resource(pdev, 0);
791 if (IS_ERR(phy->base))
792 return PTR_ERR(phy->base);
794 hi3670_pcie_get_eyeparam(phy);
802 struct device *dev = &pdev->dev;
803 struct hi3670_pcie_phy *phy;
804 struct phy *generic_phy;
807 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
808 if (!phy)
809 return -ENOMEM;
811 phy->dev = dev;
813 ret = hi3670_pcie_phy_get_resources(phy, pdev);
817 generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops);
819 dev_err(dev, "failed to create PHY\n");
823 phy_set_drvdata(generic_phy, phy);
831 .compatible = "hisilicon,hi970-pcie-phy",
847 MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");