Lines Matching +full:per +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
14 /* General registers per SerDes block */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
26 /* Per PLL registers */
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
61 /* Lane a Tx General Control Register */
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
71 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
73 /* Lane a Rx Reset Control Register */
74 #define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40) argument
80 /* Lane a Rx General Control Register */
81 #define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44) argument
91 #define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48) argument
93 #define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50) argument
94 #define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54) argument
95 #define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58) argument
97 #define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74) argument
99 #define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4) argument
104 #define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10) argument
135 struct lynx_28g_lane lane[LYNX_28G_NUM_LANE]; member
143 void __iomem *reg = priv->base + off; in lynx_28g_rmw()
152 #define lynx_28g_lane_rmw(lane, reg, val, mask) \ argument
153 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
155 #define lynx_28g_lane_read(lane, reg) \ argument
156 ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
158 ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
165 if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl)) in lynx_28g_supports_interface()
168 if (test_bit(intf, priv->pll[i].supported)) in lynx_28g_supports_interface()
182 pll = &priv->pll[i]; in lynx_28g_pll_get()
184 if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl)) in lynx_28g_pll_get()
187 if (test_bit(intf, pll->supported)) in lynx_28g_pll_get()
194 dev_WARN_ONCE(priv->dev, 1, "no pll for interface %s\n", phy_modes(intf)); in lynx_28g_pll_get()
198 static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane, in lynx_28g_lane_set_nrate() argument
202 switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) { in lynx_28g_lane_set_nrate()
208 lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK); in lynx_28g_lane_set_nrate()
209 lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK); in lynx_28g_lane_set_nrate()
219 lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK); in lynx_28g_lane_set_nrate()
220 lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK); in lynx_28g_lane_set_nrate()
231 static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane, in lynx_28g_lane_set_pll() argument
234 if (pll->id == 0) { in lynx_28g_lane_set_pll()
235 lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK); in lynx_28g_lane_set_pll()
236 lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK); in lynx_28g_lane_set_pll()
238 lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK); in lynx_28g_lane_set_pll()
239 lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK); in lynx_28g_lane_set_pll()
243 static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane) in lynx_28g_cleanup_lane() argument
245 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_cleanup_lane()
246 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_cleanup_lane()
249 switch (lane->interface) { in lynx_28g_cleanup_lane()
266 static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane) in lynx_28g_lane_set_sgmii() argument
268 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_lane_set_sgmii()
269 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_lane_set_sgmii()
272 lynx_28g_cleanup_lane(lane); in lynx_28g_lane_set_sgmii()
274 /* Setup the lane to run in SGMII */ in lynx_28g_lane_set_sgmii()
280 lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK); in lynx_28g_lane_set_sgmii()
281 lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK); in lynx_28g_lane_set_sgmii()
289 lynx_28g_lane_set_pll(lane, pll); in lynx_28g_lane_set_sgmii()
291 /* Choose the portion of clock net to be used on this lane */ in lynx_28g_lane_set_sgmii()
292 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII); in lynx_28g_lane_set_sgmii()
295 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK); in lynx_28g_lane_set_sgmii()
298 iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id)); in lynx_28g_lane_set_sgmii()
299 iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); in lynx_28g_lane_set_sgmii()
300 iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id)); in lynx_28g_lane_set_sgmii()
301 iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); in lynx_28g_lane_set_sgmii()
302 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id)); in lynx_28g_lane_set_sgmii()
303 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); in lynx_28g_lane_set_sgmii()
306 static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane) in lynx_28g_lane_set_10gbaser() argument
308 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_lane_set_10gbaser()
309 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_lane_set_10gbaser()
312 lynx_28g_cleanup_lane(lane); in lynx_28g_lane_set_10gbaser()
314 /* Enable the SXGMII lane */ in lynx_28g_lane_set_10gbaser()
320 lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK); in lynx_28g_lane_set_10gbaser()
321 lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK); in lynx_28g_lane_set_10gbaser()
329 lynx_28g_lane_set_pll(lane, pll); in lynx_28g_lane_set_10gbaser()
331 /* Choose the portion of clock net to be used on this lane */ in lynx_28g_lane_set_10gbaser()
332 lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER); in lynx_28g_lane_set_10gbaser()
335 lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK); in lynx_28g_lane_set_10gbaser()
338 iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id)); in lynx_28g_lane_set_10gbaser()
339 iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id)); in lynx_28g_lane_set_10gbaser()
340 iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id)); in lynx_28g_lane_set_10gbaser()
341 iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id)); in lynx_28g_lane_set_10gbaser()
342 iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id)); in lynx_28g_lane_set_10gbaser()
343 iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id)); in lynx_28g_lane_set_10gbaser()
348 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_power_off() local
351 if (!lane->powered_up) in lynx_28g_power_off()
355 lynx_28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ); in lynx_28g_power_off()
356 lynx_28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ); in lynx_28g_power_off()
360 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); in lynx_28g_power_off()
361 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_power_off()
365 lane->powered_up = false; in lynx_28g_power_off()
372 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_power_on() local
375 if (lane->powered_up) in lynx_28g_power_on()
378 /* Issue a reset request on the lane */ in lynx_28g_power_on()
379 lynx_28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ); in lynx_28g_power_on()
380 lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ); in lynx_28g_power_on()
384 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL); in lynx_28g_power_on()
385 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_power_on()
389 lane->powered_up = true; in lynx_28g_power_on()
396 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_set_mode() local
397 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_set_mode()
398 int powered_up = lane->powered_up; in lynx_28g_set_mode()
402 return -EOPNOTSUPP; in lynx_28g_set_mode()
404 if (lane->interface == PHY_INTERFACE_MODE_NA) in lynx_28g_set_mode()
405 return -EOPNOTSUPP; in lynx_28g_set_mode()
408 return -EOPNOTSUPP; in lynx_28g_set_mode()
410 /* If the lane is powered up, put the lane into the halt state while in lynx_28g_set_mode()
416 spin_lock(&priv->pcc_lock); in lynx_28g_set_mode()
421 lynx_28g_lane_set_sgmii(lane); in lynx_28g_set_mode()
424 lynx_28g_lane_set_10gbaser(lane); in lynx_28g_set_mode()
427 err = -EOPNOTSUPP; in lynx_28g_set_mode()
431 lane->interface = submode; in lynx_28g_set_mode()
434 spin_unlock(&priv->pcc_lock); in lynx_28g_set_mode()
436 /* Power up the lane if necessary */ in lynx_28g_set_mode()
446 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_validate() local
447 struct lynx_28g_priv *priv = lane->priv; in lynx_28g_validate()
450 return -EOPNOTSUPP; in lynx_28g_validate()
453 return -EOPNOTSUPP; in lynx_28g_validate()
460 struct lynx_28g_lane *lane = phy_get_drvdata(phy); in lynx_28g_init() local
462 /* Mark the fact that the lane was init */ in lynx_28g_init()
463 lane->init = true; in lynx_28g_init()
465 /* SerDes lanes are powered on at boot time. Any lane that is managed in lynx_28g_init()
466 * by this driver will get powered down at init time aka at dpaa2-eth in lynx_28g_init()
469 lane->powered_up = true; in lynx_28g_init()
490 pll = &priv->pll[i]; in lynx_28g_pll_read_configuration()
491 pll->priv = priv; in lynx_28g_pll_read_configuration()
492 pll->id = i; in lynx_28g_pll_read_configuration()
494 pll->rstctl = lynx_28g_pll_read(pll, PLLnRSTCTL); in lynx_28g_pll_read_configuration()
495 pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0); in lynx_28g_pll_read_configuration()
496 pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1); in lynx_28g_pll_read_configuration()
498 if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl)) in lynx_28g_pll_read_configuration()
501 switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) { in lynx_28g_pll_read_configuration()
505 __set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported); in lynx_28g_pll_read_configuration()
506 __set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported); in lynx_28g_pll_read_configuration()
510 __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported); in lynx_28g_pll_read_configuration()
524 struct lynx_28g_lane *lane; in lynx_28g_cdr_lock_check() local
529 lane = &priv->lane[i]; in lynx_28g_cdr_lock_check()
531 mutex_lock(&lane->phy->mutex); in lynx_28g_cdr_lock_check()
533 if (!lane->init || !lane->powered_up) { in lynx_28g_cdr_lock_check()
534 mutex_unlock(&lane->phy->mutex); in lynx_28g_cdr_lock_check()
538 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_cdr_lock_check()
540 lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ); in lynx_28g_cdr_lock_check()
542 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL); in lynx_28g_cdr_lock_check()
546 mutex_unlock(&lane->phy->mutex); in lynx_28g_cdr_lock_check()
548 queue_delayed_work(system_power_efficient_wq, &priv->cdr_check, in lynx_28g_cdr_lock_check()
552 static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane) in lynx_28g_lane_read_configuration() argument
556 pss = lynx_28g_lane_read(lane, LNaPSS); in lynx_28g_lane_read_configuration()
560 lane->interface = PHY_INTERFACE_MODE_SGMII; in lynx_28g_lane_read_configuration()
563 lane->interface = PHY_INTERFACE_MODE_10GBASER; in lynx_28g_lane_read_configuration()
566 lane->interface = PHY_INTERFACE_MODE_NA; in lynx_28g_lane_read_configuration()
574 int idx = args->args[0]; in lynx_28g_xlate()
577 return ERR_PTR(-EINVAL); in lynx_28g_xlate()
579 return priv->lane[idx].phy; in lynx_28g_xlate()
584 struct device *dev = &pdev->dev; in lynx_28g_probe()
589 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in lynx_28g_probe()
591 return -ENOMEM; in lynx_28g_probe()
592 priv->dev = &pdev->dev; in lynx_28g_probe()
594 priv->base = devm_platform_ioremap_resource(pdev, 0); in lynx_28g_probe()
595 if (IS_ERR(priv->base)) in lynx_28g_probe()
596 return PTR_ERR(priv->base); in lynx_28g_probe()
601 struct lynx_28g_lane *lane = &priv->lane[i]; in lynx_28g_probe() local
604 memset(lane, 0, sizeof(*lane)); in lynx_28g_probe()
606 phy = devm_phy_create(&pdev->dev, NULL, &lynx_28g_ops); in lynx_28g_probe()
610 lane->priv = priv; in lynx_28g_probe()
611 lane->phy = phy; in lynx_28g_probe()
612 lane->id = i; in lynx_28g_probe()
613 phy_set_drvdata(phy, lane); in lynx_28g_probe()
614 lynx_28g_lane_read_configuration(lane); in lynx_28g_probe()
619 spin_lock_init(&priv->pcc_lock); in lynx_28g_probe()
620 INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check); in lynx_28g_probe()
622 queue_delayed_work(system_power_efficient_wq, &priv->cdr_check, in lynx_28g_probe()
625 dev_set_drvdata(&pdev->dev, priv); in lynx_28g_probe()
626 provider = devm_of_phy_provider_register(&pdev->dev, lynx_28g_xlate); in lynx_28g_probe()
633 struct device *dev = &pdev->dev; in lynx_28g_remove()
636 cancel_delayed_work_sync(&priv->cdr_check); in lynx_28g_remove()
640 { .compatible = "fsl,lynx-28g" },
649 .name = "lynx-28g",