Lines Matching +full:20 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
35 #define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24)
36 #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25)
37 #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26)
38 #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27)
52 #define PHY_CTRL_R13_LOAD_STAT BIT(14)
53 #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15)
54 #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16)
55 #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21)
56 #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22)
57 #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23)
58 #define PHY_CTRL_R13_I_C2L_HS_EN BIT(24)
59 #define PHY_CTRL_R13_I_C2L_FS_EN BIT(25)
60 #define PHY_CTRL_R13_I_C2L_LS_EN BIT(26)
61 #define PHY_CTRL_R13_I_C2L_HS_OE BIT(27)
62 #define PHY_CTRL_R13_I_C2L_FS_OE BIT(28)
63 #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29)
64 #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30)
67 #define PHY_CTRL_R14_I_RDP_EN BIT(0)
68 #define PHY_CTRL_R14_I_RPU_SW1_EN BIT(1)
70 #define PHY_CTRL_R14_PG_RSTN BIT(4)
71 #define PHY_CTRL_R14_I_C2L_DATA_16_8 BIT(5)
72 #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO BIT(6)
80 #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20)
81 #define PHY_CTRL_R16_MPLL_SDM_EN BIT(21)
82 #define PHY_CTRL_R16_MPLL_LOAD BIT(22)
83 #define PHY_CTRL_R16_MPLL_DCO_SDM_EN BIT(23)
85 #define PHY_CTRL_R16_MPLL_LOCK_F BIT(26)
86 #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27)
87 #define PHY_CTRL_R16_MPLL_EN BIT(28)
88 #define PHY_CTRL_R16_MPLL_RESET BIT(29)
89 #define PHY_CTRL_R16_MPLL_LOCK BIT(30)
90 #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31)
94 #define PHY_CTRL_R17_MPLL_FIX_EN BIT(16)
96 #define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20)
97 #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23)
105 #define PHY_CTRL_R18_MPLL_DCO_M_EN BIT(12)
106 #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL BIT(13)
114 #define PHY_CTRL_R18_MPLL_ACG_RANGE BIT(31)
118 #define PHY_CTRL_R20_USB2_IDDET_EN BIT(0)
120 #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4)
121 #define PHY_CTRL_R20_USB2_AMON_EN BIT(5)
122 #define PHY_CTRL_R20_USB2_CAL_CODE_R5 BIT(6)
123 #define PHY_CTRL_R20_BYPASS_OTG_DET BIT(7)
124 #define PHY_CTRL_R20_USB2_DMON_EN BIT(8)
126 #define PHY_CTRL_R20_USB2_EDGE_DRV_EN BIT(13)
128 #define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 GENMASK(20, 16)
129 #define PHY_CTRL_R20_USB2_BGR_START BIT(21)
132 #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 BIT(31)
135 #define PHY_CTRL_R21_USB2_BGR_FORCE BIT(0)
136 #define PHY_CTRL_R21_USB2_CAL_ACK_EN BIT(1)
137 #define PHY_CTRL_R21_USB2_OTG_ACA_EN BIT(2)
138 #define PHY_CTRL_R21_USB2_TX_STRG_PD BIT(3)
141 #define PHY_CTRL_R21_BYPASS_UTMI_REG GENMASK(25, 20)
175 ret = clk_prepare_enable(priv->clk); in phy_meson_g12a_usb2_init()
179 ret = reset_control_reset(priv->reset); in phy_meson_g12a_usb2_init()
181 clk_disable_unprepare(priv->clk); in phy_meson_g12a_usb2_init()
188 regmap_update_bits(priv->regmap, PHY_CTRL_R21, in phy_meson_g12a_usb2_init()
191 /* PLL Setup : 24MHz * 20 / 1 = 480MHz */ in phy_meson_g12a_usb2_init()
192 regmap_write(priv->regmap, PHY_CTRL_R16, in phy_meson_g12a_usb2_init()
193 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
201 regmap_write(priv->regmap, PHY_CTRL_R17, in phy_meson_g12a_usb2_init()
220 if (priv->soc_id == MESON_SOC_A1) in phy_meson_g12a_usb2_init()
223 regmap_write(priv->regmap, PHY_CTRL_R18, value); in phy_meson_g12a_usb2_init()
228 regmap_write(priv->regmap, PHY_CTRL_R16, in phy_meson_g12a_usb2_init()
229 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
237 regmap_write(priv->regmap, PHY_CTRL_R20, in phy_meson_g12a_usb2_init()
247 if (priv->soc_id == MESON_SOC_G12A) in phy_meson_g12a_usb2_init()
248 regmap_write(priv->regmap, PHY_CTRL_R4, in phy_meson_g12a_usb2_init()
255 else if (priv->soc_id == MESON_SOC_A1) { in phy_meson_g12a_usb2_init()
256 regmap_write(priv->regmap, PHY_CTRL_R21, in phy_meson_g12a_usb2_init()
262 regmap_write(priv->regmap, PHY_CTRL_R13, in phy_meson_g12a_usb2_init()
267 regmap_write(priv->regmap, PHY_CTRL_R3, in phy_meson_g12a_usb2_init()
272 if (priv->soc_id == MESON_SOC_G12A) { in phy_meson_g12a_usb2_init()
274 regmap_write(priv->regmap, PHY_CTRL_R14, 0); in phy_meson_g12a_usb2_init()
275 regmap_write(priv->regmap, PHY_CTRL_R13, in phy_meson_g12a_usb2_init()
288 ret = reset_control_reset(priv->reset); in phy_meson_g12a_usb2_exit()
290 clk_disable_unprepare(priv->clk); in phy_meson_g12a_usb2_exit()
304 struct device *dev = &pdev->dev; in phy_meson_g12a_usb2_probe()
313 return -ENOMEM; in phy_meson_g12a_usb2_probe()
315 priv->dev = dev; in phy_meson_g12a_usb2_probe()
322 priv->soc_id = (uintptr_t)of_device_get_match_data(&pdev->dev); in phy_meson_g12a_usb2_probe()
324 priv->regmap = devm_regmap_init_mmio(dev, base, in phy_meson_g12a_usb2_probe()
326 if (IS_ERR(priv->regmap)) in phy_meson_g12a_usb2_probe()
327 return PTR_ERR(priv->regmap); in phy_meson_g12a_usb2_probe()
329 priv->clk = devm_clk_get(dev, "xtal"); in phy_meson_g12a_usb2_probe()
330 if (IS_ERR(priv->clk)) in phy_meson_g12a_usb2_probe()
331 return PTR_ERR(priv->clk); in phy_meson_g12a_usb2_probe()
333 priv->reset = devm_reset_control_get(dev, "phy"); in phy_meson_g12a_usb2_probe()
334 if (IS_ERR(priv->reset)) in phy_meson_g12a_usb2_probe()
335 return PTR_ERR(priv->reset); in phy_meson_g12a_usb2_probe()
337 ret = reset_control_deassert(priv->reset); in phy_meson_g12a_usb2_probe()
356 .compatible = "amlogic,g12a-usb2-phy",
360 .compatible = "amlogic,a1-usb2-phy",
370 .name = "phy-meson-g12a-usb2",