123 /* The DTC node is where the magic happens */
128 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
130 #define CMN_DT_PMEVCNT(dtc, n)		((dtc)->pmu_base + _CMN_DT_CNT_REG(n))  argument
131 #define CMN_DT_PMCCNTR(dtc)		((dtc)->pmu_base + 0x40)  argument
133 #define CMN_DT_PMEVCNTSR(dtc, n)	((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n))  argument
134 #define CMN_DT_PMCCNTRSR(dtc)		((dtc)->pmu_base + 0x90)  argument
136 #define CMN_DT_PMCR(dtc)		((dtc)->pmu_base + 0x100)  argument
141 #define CMN_DT_PMOVSR(dtc)		((dtc)->pmu_base + 0x118)  argument
142 #define CMN_DT_PMOVSR_CLR(dtc)		((dtc)->pmu_base + 0x120)  argument
144 #define CMN_DT_PMSSR(dtc)		((dtc)->pmu_base + 0x128)  argument
147 #define CMN_DT_PMSRR(dtc)		((dtc)->pmu_base + 0x130)  argument
154  * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
292 	s8 dtc;  member
356 	struct arm_cmn_dtc *dtc;  member
551 			s8 dtc = xp[x].dtc;  in arm_cmn_map_show()  local
553 			if (dtc < 0)  in arm_cmn_map_show()
554 				seq_puts(s, " DTC ?? |");  in arm_cmn_map_show()
556 				seq_printf(s, " DTC %d  |", dtc);  in arm_cmn_map_show()
618 /* @i is the DTC number, @idx is the counter index on that DTC */
1383 				 unsigned int dtc, int wp_idx,  in arm_cmn_claim_wp_idx()  argument
1388 	dtm->wp_event[wp_idx] = hw->dtc_idx[dtc];  in arm_cmn_claim_wp_idx()
1424 		writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0]));  in arm_cmn_set_state()
1433 			       CMN_DT_PMCR(&cmn->dtc[0]));  in arm_cmn_clear_state()
1466 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)  in arm_cmn_read_cc()  argument
1468 	void __iomem *pmccntr = CMN_DT_PMCCNTR(dtc);  in arm_cmn_read_cc()
1475 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)  in arm_cmn_read_counter()  argument
1477 	void __iomem *pmevcnt = CMN_DT_PMEVCNT(dtc, idx);  in arm_cmn_read_counter()
1491 		writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx));  in arm_cmn_init_counter()
1492 		cmn->dtc[i].counters[idx] = event;  in arm_cmn_init_counter()
1507 		delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]);  in arm_cmn_event_read()
1518 		new = arm_cmn_read_counter(cmn->dtc + i, idx);  in arm_cmn_event_read()
1574 		struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0];  in arm_cmn_event_start()  local
1577 			       dtc->base + CMN_DT_DTC_CTL);  in arm_cmn_event_start()
1578 		writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc));  in arm_cmn_event_start()
1579 		dtc->cc_active = true;  in arm_cmn_event_start()
1608 		struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0];  in arm_cmn_event_stop()  local
1610 		dtc->cc_active = false;  in arm_cmn_event_stop()
1611 		writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);  in arm_cmn_event_stop()
1667 	for_each_hw_dtc_idx(hw, dtc, idx)  in arm_cmn_val_add_event()
1668 		val->dtc_count[dtc]++;  in arm_cmn_val_add_event()
1717 	for_each_hw_dtc_idx(hw, dtc, idx)  in arm_cmn_validate_group()
1718 		if (val->dtc_count[dtc] == CMN_DT_NUM_COUNTERS)  in arm_cmn_validate_group()
1785 	/* DTC events (i.e. cycles) already have everything they need */  in arm_cmn_event_init()
1824 		if (dn->dtc < 0)  in arm_cmn_event_init()
1827 			hw->dtc_idx[dn->dtc] = 0;  in arm_cmn_event_init()
1867 		cmn->dtc[j].counters[idx] = NULL;  in arm_cmn_event_clear()
1879 		while (cmn->dtc[i].cycles)  in arm_cmn_event_add()
1883 		cmn->dtc[i].cycles = event;  in arm_cmn_event_add()
1897 			while (cmn->dtc[j].counters[idx])  in arm_cmn_event_add()
1907 		unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0);  in arm_cmn_event_add()
1929 					CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp]))  in arm_cmn_event_add()
1982 		cmn->dtc[hw->dtc_idx[0]].cycles = NULL;  in arm_cmn_event_del()
2015 		irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));  in arm_cmn_migrate()
2055 	struct arm_cmn_dtc *dtc = dev_id;  in arm_cmn_handle_irq()  local
2059 		u32 status = readl_relaxed(CMN_DT_PMOVSR(dtc));  in arm_cmn_handle_irq()
2066 				if (WARN_ON(!dtc->counters[i]))  in arm_cmn_handle_irq()
2068 				delta = (u64)arm_cmn_read_counter(dtc, i) << 16;  in arm_cmn_handle_irq()
2069 				local64_add(delta, &dtc->counters[i]->count);  in arm_cmn_handle_irq()
2075 			if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {  in arm_cmn_handle_irq()
2076 				delta = arm_cmn_read_cc(dtc);  in arm_cmn_handle_irq()
2077 				local64_add(delta, &dtc->cycles->count);  in arm_cmn_handle_irq()
2081 		writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc));  in arm_cmn_handle_irq()
2083 		if (!dtc->irq_friend)  in arm_cmn_handle_irq()
2085 		dtc += dtc->irq_friend;  in arm_cmn_handle_irq()
2095 		irq = cmn->dtc[i].irq;  in arm_cmn_init_irqs()
2097 			if (cmn->dtc[j].irq == irq) {  in arm_cmn_init_irqs()
2098 				cmn->dtc[j].irq_friend = i - j;  in arm_cmn_init_irqs()
2104 				       dev_name(cmn->dev), &cmn->dtc[i]);  in arm_cmn_init_irqs()
2133 	struct arm_cmn_dtc *dtc = cmn->dtc + idx;  in arm_cmn_init_dtc()  local
2135 	dtc->pmu_base = dn->pmu_base;  in arm_cmn_init_dtc()
2136 	dtc->base = dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn);  in arm_cmn_init_dtc()
2137 	dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);  in arm_cmn_init_dtc()
2138 	if (dtc->irq < 0)  in arm_cmn_init_dtc()
2139 		return dtc->irq;  in arm_cmn_init_dtc()
2141 	writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);  in arm_cmn_init_dtc()
2142 	writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR(dtc));  in arm_cmn_init_dtc()
2143 	writeq_relaxed(0, CMN_DT_PMCCNTR(dtc));  in arm_cmn_init_dtc()
2144 	writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc));  in arm_cmn_init_dtc()
2165 	cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);  in arm_cmn_init_dtcs()
2166 	if (!cmn->dtc)  in arm_cmn_init_dtcs()
2178 		dn->dtc = xp->dtc;  in arm_cmn_init_dtcs()
2354 			xp->dtc = -1;  in arm_cmn_discover()
2356 			xp->dtc = arm_cmn_dtc_domain(cmn, xp_region);  in arm_cmn_discover()
2627 	writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);  in arm_cmn_remove()