Lines Matching +full:system +full:- +full:cache +full:- +full:controller

1 # SPDX-License-Identifier: GPL-2.0-only
14 	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 	  If compiled as a module, it will be called arm-cci.
20 	bool "support CCI-400"
25 	  CCI-400 provides 4 independent event counters counting events related
29 	bool "support CCI-500/CCI-550"
33 	  CCI-500/CCI-550 both provide 8 independent event counters, which can
41 	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 	tristate "Arm CMN-600 PMU support"
48 	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 	tristate "Arm NI-700 PMU support"
55 	  Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
63 	  Say y if you want to use CPU performance monitors on ARM-based
80 	bool "RISC-V PMU framework"
83 	  Say y if you want to use CPU performance monitors on RISCV-based
90 	bool "RISC-V legacy PMU implementation"
94 	  implementation on RISC-V based systems. This only allows counting
100 	bool "RISC-V PMU based on SBI PMU extension"
104 	  using SBI PMU extension on RISC-V based systems. This option provides
115 	   an L3 memory system. The L3 cache events are added into perf event
116 	   subsystem, allowing monitoring of various L3 cache perf events.
127 	  non-standard behaviour via the regular SBI PMU driver and
162 	  system, control logic. The PMU allows counting various events related
182 	bool "Qualcomm Technologies L2-cache PMU"
186 	  Provides support for the L2 cache performance monitor unit (PMU)
188 	  Adds the L2 cache PMU into the perf events subsystem for
189 	  monitoring L2 cache events.
192 	bool "Qualcomm Technologies L3-cache PMU"
196 	   Provides support for the L3 cache performance monitor unit (PMU)
198 	   Adds the L3 cache PMU into the perf events subsystem for
199 	   monitoring L3 cache events.
208 	   The SoC has PMU support in its L3 cache controller (L3C) and
209 	   in the DDR4 Memory Controller (DMC).
213         bool "APM X-Gene SoC PMU"
216           Say y if you want to use APM X-Gene SoC performance monitors.
227 	tristate "Enable PMU support for the ARM DMC-620 memory controller"
230 	  Support for PMU events monitoring on the ARM DMC-620 memory
231 	  controller.
234 	tristate "Marvell CN10K LLC-TAD PMU"
237 	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
244 	  Provides support for the non-architectural CPU PMUs present on
248 	tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
252 	  Sub-system.