46 	MRPC_IDLE = 0,
173 		memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);  in mrpc_cmd_submit()
201 	return 0;  in mrpc_queue_cmd()
215 	stdev->mrpc_busy = 0;  in mrpc_cleanup_cmd()
241 	stuser->return_code = 0;  in mrpc_complete_cmd()
251 	if (stuser->return_code != 0)  in mrpc_complete_cmd()
356 	buf[len + 1] = 0;  in io_string_show()
358 	for (i = len - 1; i > 0; i--) {  in io_string_show()
362 		buf[i + 1] = 0;  in io_string_show()
483 	return 0;  in switchtec_dev_open()
492 	return 0;  in switchtec_dev_release()
505 	return 0;  in lock_mutex_and_test_alive()
590 		if (rc < 0)  in switchtec_dev_read()
640 	__poll_t ret = 0;  in switchtec_dev_poll()
662 	struct switchtec_ioctl_flash_info info = {0};  in ioctl_flash_info()
678 	return 0;  in ioctl_flash_info()
725 		set_fw_info_part(info, &fi->vendor[0]);  in flash_part_info_gen3()
755 	return 0;  in flash_part_info_gen3()
832 		set_fw_info_part(info, &fi->vendor[0]);  in flash_part_info_gen4()
859 	return 0;  in flash_part_info_gen4()
866 	struct switchtec_ioctl_flash_part_info info = {0};  in ioctl_flash_part_info()
886 	return 0;  in ioctl_flash_part_info()
897 	int ret = 0;  in ioctl_event_summary()
907 	for (i = 0; i < stdev->partition_count; i++) {  in ioctl_event_summary()
912 	for (i = 0; i < stdev->pff_csr_count; i++) {  in ioctl_event_summary()
998 	if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)  in event_hdr_addr()
1006 		else if (index < 0 || index >= stdev->partition_count)  in event_hdr_addr()
1009 		if (index < 0 || index >= stdev->pff_csr_count)  in event_hdr_addr()
1031 	for (i = 0; i < ARRAY_SIZE(ctl->data); i++)  in event_ctl()
1035 	ctl->count = (hdr >> 5) & 0xFF;  in event_ctl()
1059 	ctl->flags = 0;  in event_ctl()
1069 	return 0;  in event_ctl()
1100 		for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) {  in ioctl_event_ctl()
1103 			if (ret < 0 && ret != -EOPNOTSUPP)  in ioctl_event_ctl()
1108 		if (ret < 0)  in ioctl_event_ctl()
1115 	return 0;  in ioctl_event_ctl()
1130 	for (part = 0; part < stdev->partition_count; part++) {  in ioctl_pff_to_port()
1136 			p.port = 0;  in ioctl_pff_to_port()
1140 		reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;  in ioctl_pff_to_port()
1146 		for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {  in ioctl_pff_to_port()
1162 	return 0;  in ioctl_pff_to_port()
1182 	case 0:  in ioctl_port_to_pff()
1186 		p.pff = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;  in ioctl_port_to_pff()
1200 	return 0;  in ioctl_port_to_pff()
1274 	int occurred = 0;  in check_link_state_events()
1276 	for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in check_link_state_events()
1279 		count = (reg >> 5) & 0xFF;  in check_link_state_events()
1295 	for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in enable_link_state_events()
1359 	stdev->mrpc_busy = 0;  in stdev_create()
1364 	atomic_set(&stdev->event_cnt, 0);  in stdev_create()
1374 	if (minor < 0) {  in stdev_create()
1404 		return 0;  in mask_event()
1407 		return 0;  in mask_event()
1419 	int count = 0;  in mask_all_events()
1422 		for (idx = 0; idx < stdev->partition_count; idx++)  in mask_all_events()
1425 		for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in mask_all_events()
1432 		count += mask_event(stdev, eid, 0);  in mask_all_events()
1443 	int eid, event_count = 0;  in switchtec_event_isr()
1455 	for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {  in switchtec_event_isr()
1500 	if (nvecs < 0)  in switchtec_init_isr()
1504 	if (event_irq < 0 || event_irq >= nvecs)  in switchtec_init_isr()
1508 	if (event_irq < 0)  in switchtec_init_isr()
1512 				switchtec_event_isr, 0,  in switchtec_init_isr()
1522 	if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs)  in switchtec_init_isr()
1526 	if (dma_mrpc_irq < 0)  in switchtec_init_isr()
1530 				switchtec_dma_mrpc_isr, 0,  in switchtec_init_isr()
1542 	for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {  in init_pff()
1554 	reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;  in init_pff()
1558 	for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {  in init_pff()
1583 	res_start = pci_resource_start(pdev, 0);  in switchtec_init_pci()
1584 	res_len = pci_resource_len(pdev, 0);  in switchtec_init_pci()
1628 		return 0;  in switchtec_init_pci()
1630 	if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)  in switchtec_init_pci()
1631 		return 0;  in switchtec_init_pci()
1640 	return 0;  in switchtec_init_pci()
1646 		iowrite32(0, &stdev->mmio_mrpc->dma_en);  in switchtec_exit_pci()
1648 		writeq(0, &stdev->mmio_mrpc->dma_addr);  in switchtec_exit_pci()
1694 	return 0;  in switchtec_pci_probe()
1729 		.class_mask = 0xFFFFFFFF, \
1738 		.class_mask = 0xFFFFFFFF, \
1743 	SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3),  /* PFX 24xG3 */
1744 	SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3),  /* PFX 32xG3 */
1745 	SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3),  /* PFX 48xG3 */
1746 	SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3),  /* PFX 64xG3 */
1747 	SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3),  /* PFX 80xG3 */
1748 	SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3),  /* PFX 96xG3 */
1749 	SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3),  /* PSX 24xG3 */
1750 	SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3),  /* PSX 32xG3 */
1751 	SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3),  /* PSX 48xG3 */
1752 	SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3),  /* PSX 64xG3 */
1753 	SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3),  /* PSX 80xG3 */
1754 	SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3),  /* PSX 96xG3 */
1755 	SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3),  /* PAX 24XG3 */
1756 	SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3),  /* PAX 32XG3 */
1757 	SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3),  /* PAX 48XG3 */
1758 	SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3),  /* PAX 64XG3 */
1759 	SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3),  /* PAX 80XG3 */
1760 	SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3),  /* PAX 96XG3 */
1761 	SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3),  /* PFXL 24XG3 */
1762 	SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3),  /* PFXL 32XG3 */
1763 	SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3),  /* PFXL 48XG3 */
1764 	SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3),  /* PFXL 64XG3 */
1765 	SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3),  /* PFXL 80XG3 */
1766 	SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3),  /* PFXL 96XG3 */
1767 	SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3),  /* PFXI 24XG3 */
1768 	SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3),  /* PFXI 32XG3 */
1769 	SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3),  /* PFXI 48XG3 */
1770 	SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3),  /* PFXI 64XG3 */
1771 	SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3),  /* PFXI 80XG3 */
1772 	SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3),  /* PFXI 96XG3 */
1773 	SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4),  /* PFX 100XG4 */
1774 	SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4),  /* PFX 84XG4 */
1775 	SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4),  /* PFX 68XG4 */
1776 	SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4),  /* PFX 52XG4 */
1777 	SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4),  /* PFX 36XG4 */
1778 	SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4),  /* PFX 28XG4 */
1779 	SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4),  /* PSX 100XG4 */
1780 	SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4),  /* PSX 84XG4 */
1781 	SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4),  /* PSX 68XG4 */
1782 	SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4),  /* PSX 52XG4 */
1783 	SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4),  /* PSX 36XG4 */
1784 	SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4),  /* PSX 28XG4 */
1785 	SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4),  /* PAX 100XG4 */
1786 	SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4),  /* PAX 84XG4 */
1787 	SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4),  /* PAX 68XG4 */
1788 	SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4),  /* PAX 52XG4 */
1789 	SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4),  /* PAX 36XG4 */
1790 	SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4),  /* PAX 28XG4 */
1791 	SWITCHTEC_PCI_DEVICE(0x4352, SWITCHTEC_GEN4),  /* PFXA 52XG4 */
1792 	SWITCHTEC_PCI_DEVICE(0x4336, SWITCHTEC_GEN4),  /* PFXA 36XG4 */
1793 	SWITCHTEC_PCI_DEVICE(0x4328, SWITCHTEC_GEN4),  /* PFXA 28XG4 */
1794 	SWITCHTEC_PCI_DEVICE(0x4452, SWITCHTEC_GEN4),  /* PSXA 52XG4 */
1795 	SWITCHTEC_PCI_DEVICE(0x4436, SWITCHTEC_GEN4),  /* PSXA 36XG4 */
1796 	SWITCHTEC_PCI_DEVICE(0x4428, SWITCHTEC_GEN4),  /* PSXA 28XG4 */
1797 	SWITCHTEC_PCI_DEVICE(0x4552, SWITCHTEC_GEN4),  /* PAXA 52XG4 */
1798 	SWITCHTEC_PCI_DEVICE(0x4536, SWITCHTEC_GEN4),  /* PAXA 36XG4 */
1799 	SWITCHTEC_PCI_DEVICE(0x4528, SWITCHTEC_GEN4),  /* PAXA 28XG4 */
1800 	SWITCHTEC_PCI_DEVICE(0x5000, SWITCHTEC_GEN5),  /* PFX 100XG5 */
1801 	SWITCHTEC_PCI_DEVICE(0x5084, SWITCHTEC_GEN5),  /* PFX 84XG5 */
1802 	SWITCHTEC_PCI_DEVICE(0x5068, SWITCHTEC_GEN5),  /* PFX 68XG5 */
1803 	SWITCHTEC_PCI_DEVICE(0x5052, SWITCHTEC_GEN5),  /* PFX 52XG5 */
1804 	SWITCHTEC_PCI_DEVICE(0x5036, SWITCHTEC_GEN5),  /* PFX 36XG5 */
1805 	SWITCHTEC_PCI_DEVICE(0x5028, SWITCHTEC_GEN5),  /* PFX 28XG5 */
1806 	SWITCHTEC_PCI_DEVICE(0x5100, SWITCHTEC_GEN5),  /* PSX 100XG5 */
1807 	SWITCHTEC_PCI_DEVICE(0x5184, SWITCHTEC_GEN5),  /* PSX 84XG5 */
1808 	SWITCHTEC_PCI_DEVICE(0x5168, SWITCHTEC_GEN5),  /* PSX 68XG5 */
1809 	SWITCHTEC_PCI_DEVICE(0x5152, SWITCHTEC_GEN5),  /* PSX 52XG5 */
1810 	SWITCHTEC_PCI_DEVICE(0x5136, SWITCHTEC_GEN5),  /* PSX 36XG5 */
1811 	SWITCHTEC_PCI_DEVICE(0x5128, SWITCHTEC_GEN5),  /* PSX 28XG5 */
1812 	SWITCHTEC_PCI_DEVICE(0x5200, SWITCHTEC_GEN5),  /* PAX 100XG5 */
1813 	SWITCHTEC_PCI_DEVICE(0x5284, SWITCHTEC_GEN5),  /* PAX 84XG5 */
1814 	SWITCHTEC_PCI_DEVICE(0x5268, SWITCHTEC_GEN5),  /* PAX 68XG5 */
1815 	SWITCHTEC_PCI_DEVICE(0x5252, SWITCHTEC_GEN5),  /* PAX 52XG5 */
1816 	SWITCHTEC_PCI_DEVICE(0x5236, SWITCHTEC_GEN5),  /* PAX 36XG5 */
1817 	SWITCHTEC_PCI_DEVICE(0x5228, SWITCHTEC_GEN5),  /* PAX 28XG5 */
1818 	SWITCHTEC_PCI_DEVICE(0x5300, SWITCHTEC_GEN5),  /* PFXA 100XG5 */
1819 	SWITCHTEC_PCI_DEVICE(0x5384, SWITCHTEC_GEN5),  /* PFXA 84XG5 */
1820 	SWITCHTEC_PCI_DEVICE(0x5368, SWITCHTEC_GEN5),  /* PFXA 68XG5 */
1821 	SWITCHTEC_PCI_DEVICE(0x5352, SWITCHTEC_GEN5),  /* PFXA 52XG5 */
1822 	SWITCHTEC_PCI_DEVICE(0x5336, SWITCHTEC_GEN5),  /* PFXA 36XG5 */
1823 	SWITCHTEC_PCI_DEVICE(0x5328, SWITCHTEC_GEN5),  /* PFXA 28XG5 */
1824 	SWITCHTEC_PCI_DEVICE(0x5400, SWITCHTEC_GEN5),  /* PSXA 100XG5 */
1825 	SWITCHTEC_PCI_DEVICE(0x5484, SWITCHTEC_GEN5),  /* PSXA 84XG5 */
1826 	SWITCHTEC_PCI_DEVICE(0x5468, SWITCHTEC_GEN5),  /* PSXA 68XG5 */
1827 	SWITCHTEC_PCI_DEVICE(0x5452, SWITCHTEC_GEN5),  /* PSXA 52XG5 */
1828 	SWITCHTEC_PCI_DEVICE(0x5436, SWITCHTEC_GEN5),  /* PSXA 36XG5 */
1829 	SWITCHTEC_PCI_DEVICE(0x5428, SWITCHTEC_GEN5),  /* PSXA 28XG5 */
1830 	SWITCHTEC_PCI_DEVICE(0x5500, SWITCHTEC_GEN5),  /* PAXA 100XG5 */
1831 	SWITCHTEC_PCI_DEVICE(0x5584, SWITCHTEC_GEN5),  /* PAXA 84XG5 */
1832 	SWITCHTEC_PCI_DEVICE(0x5568, SWITCHTEC_GEN5),  /* PAXA 68XG5 */
1833 	SWITCHTEC_PCI_DEVICE(0x5552, SWITCHTEC_GEN5),  /* PAXA 52XG5 */
1834 	SWITCHTEC_PCI_DEVICE(0x5536, SWITCHTEC_GEN5),  /* PAXA 36XG5 */
1835 	SWITCHTEC_PCI_DEVICE(0x5528, SWITCHTEC_GEN5),  /* PAXA 28XG5 */
1836 	{0}
1851 	rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices,  in switchtec_init()
1866 	return 0;  in switchtec_init()