Lines Matching +full:0 +full:xc01
92 * Return 0 if the link has been successfully retrained. Return an error
98 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
268 u8 cls = 0; in pci_apply_final_quirks()
302 return 0; in pci_apply_final_quirks()
340 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
344 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
390 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
391 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
394 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
396 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
405 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { in quirk_nopcipci()
416 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
417 if (rev == 0x13) { in quirk_nopciamd()
428 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { in quirk_triton()
461 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
465 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
473 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
489 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
492 * Set bit 4 and bit 5 of byte 76 to 0x01 in quirk_vialatency()
497 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
513 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { in quirk_viaetbf()
522 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { in quirk_vsfx()
531 * space. Latency must be set to 0xA and Triton workaround applied too.
536 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { in quirk_alimagik()
547 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { in quirk_natoma()
560 * This chip can cause PCI parity errors if config register 0xA0 is read
565 dev->cfg_size = 0xA0; in quirk_citrine()
570 * This chip can cause bus lockups if config addresses above 0x600
575 dev->cfg_size = 0x600; in quirk_nfp6000()
587 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in quirk_extend_bar_to_page()
592 resource_set_range(r, 0, PAGE_SIZE); in quirk_extend_bar_to_page()
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
607 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
611 resource_set_range(r, 0, SZ_64M); in quirk_s3_64M()
657 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
658 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
700 * between 0x3b0->0x3bb or read 0x3d3
704 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
706 request_region(0x3b0, 0x0C, "RadeonIGP"); in quirk_ati_exploding_mce()
707 request_region(0x3d3, 0x01, "RadeonIGP"); in quirk_ati_exploding_mce()
713 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
718 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
761 PCI_CLASS_SERIAL_USB_XHCI, 0,
771 * 0xE0 (64 bytes of ACPI registers)
772 * 0xE2 (32 bytes of SMB registers)
776 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
777 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
790 base = devres & 0xffff; in piix4_io_quirk()
800 * reserve it (at least if it's in the 0x1000+ range), but in piix4_io_quirk()
815 base = devres & 0xffff0000; in piix4_mem_quirk()
816 mask = (devres & 0x3f) << 16; in piix4_mem_quirk()
835 * 0x40 (64 bytes of ACPI registers)
836 * 0x90 (16 bytes of SMB registers)
843 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
844 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
847 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
849 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
850 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
856 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
857 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
861 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
862 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
864 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
865 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
870 #define ICH_PMBASE 0x40
871 #define ICH_ACPI_CNTL 0x44
872 #define ICH4_ACPI_EN 0x10
873 #define ICH6_ACPI_EN 0x80
874 #define ICH4_GPIOBASE 0x58
875 #define ICH4_GPIO_CNTL 0x5c
876 #define ICH4_GPIO_EN 0x10
877 #define ICH6_GPIOBASE 0x48
878 #define ICH6_GPIO_CNTL 0x4c
879 #define ICH6_GPIO_EN 0x10
883 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
884 * 0x58 (64 bytes of GPIO I/O space)
944 base = val & 0xfffc; in ich6_lpc_generic_decode()
971 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
972 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
990 base = val & 0xfffc; in ich7_lpc_generic_decode()
991 mask = (val >> 16) & 0xfc; in ich7_lpc_generic_decode()
1008 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
1009 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
1010 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
1011 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
1029 * 0x48 or 0x20 (256 bytes of ACPI registers)
1033 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1034 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
1041 * 0x48 (256 bytes of ACPI registers)
1042 * 0x70 (128 bytes of hardware monitoring register)
1043 * 0x90 (16 bytes of SMB registers)
1049 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
1052 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
1058 * 0x88 (128 bytes of power management registers)
1059 * 0xd0 (16 bytes of SMB registers)
1063 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
1064 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
1103 tmp = 0; /* nothing routed to external APIC */ in quirk_via_ioapic()
1105 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1110 /* Offset 0x58: External APIC IRQ output control */ in quirk_via_ioapic()
1111 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
1127 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
1130 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
1147 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1160 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1172 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1191 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1192 pci_read_config_byte(d, 0x42, &irq); in quirk_via_acpi()
1193 irq &= 0xf; in quirk_via_acpi()
1266 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1291 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
1304 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
1321 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
1325 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
1326 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
1328 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1346 resource_set_range(r, 0, SZ_16M); in quirk_dunord()
1353 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1372 pci_read_config_byte(dev, 0x41, ®); in quirk_mediagx_master()
1375 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1377 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1392 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1394 pci_read_config_word(pdev, 0x40, &config); in quirk_disable_pxb()
1397 pci_write_config_word(pdev, 0x40, config); in quirk_disable_pxb()
1410 if (tmp == 0x01) { in quirk_amd_ide_mode()
1411 pci_read_config_byte(pdev, 0x40, &tmp); in quirk_amd_ide_mode()
1412 pci_write_config_byte(pdev, 0x40, tmp|1); in quirk_amd_ide_mode()
1413 pci_write_config_byte(pdev, 0x9, 1); in quirk_amd_ide_mode()
1414 pci_write_config_byte(pdev, 0xa, 6); in quirk_amd_ide_mode()
1415 pci_write_config_byte(pdev, 0x40, tmp); in quirk_amd_ide_mode()
1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1493 * package 2.7.0 for details)
1520 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1521 case 0x8070: /* P4B */ in asus_hides_smbus_hostbridge()
1522 case 0x8088: /* P4B533 */ in asus_hides_smbus_hostbridge()
1523 case 0x1626: /* L3C notebook */ in asus_hides_smbus_hostbridge()
1528 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1529 case 0x80b2: /* P4PE */ in asus_hides_smbus_hostbridge()
1530 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1535 case 0x8030: /* P4T533 */ in asus_hides_smbus_hostbridge()
1540 case 0x8070: /* P4G8X Deluxe */ in asus_hides_smbus_hostbridge()
1545 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1550 case 0x1751: /* M2N notebook */ in asus_hides_smbus_hostbridge()
1551 case 0x1821: /* M5N notebook */ in asus_hides_smbus_hostbridge()
1552 case 0x1897: /* A6L notebook */ in asus_hides_smbus_hostbridge()
1557 case 0x184b: /* W1N notebook */ in asus_hides_smbus_hostbridge()
1558 case 0x186a: /* M6Ne notebook */ in asus_hides_smbus_hostbridge()
1563 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1568 case 0x1882: /* M6V notebook */ in asus_hides_smbus_hostbridge()
1569 case 0x1977: /* A6VA notebook */ in asus_hides_smbus_hostbridge()
1575 case 0x088C: /* HP Compaq nc8000 */ in asus_hides_smbus_hostbridge()
1576 case 0x0890: /* HP Compaq nc6000 */ in asus_hides_smbus_hostbridge()
1581 case 0x12bc: /* HP D330L */ in asus_hides_smbus_hostbridge()
1582 case 0x12bd: /* HP D530 */ in asus_hides_smbus_hostbridge()
1583 case 0x006a: /* HP Compaq nx9500 */ in asus_hides_smbus_hostbridge()
1588 case 0x12bf: /* HP xw4100 */ in asus_hides_smbus_hostbridge()
1594 case 0xC00C: /* Samsung P35 notebook */ in asus_hides_smbus_hostbridge()
1600 case 0x0058: /* Compaq Evo N620c */ in asus_hides_smbus_hostbridge()
1605 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1613 case 0x00b8: /* Compaq Evo D510 CMT */ in asus_hides_smbus_hostbridge()
1614 case 0x00b9: /* Compaq Evo D510 SFF */ in asus_hides_smbus_hostbridge()
1615 case 0x00ba: /* Compaq Evo D510 USDT */ in asus_hides_smbus_hostbridge()
1625 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ in asus_hides_smbus_hostbridge()
1655 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1656 if (val & 0x8) { in asus_hides_smbus_lpc()
1657 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1658 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1659 if (val & 0x8) in asus_hides_smbus_lpc()
1660 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1691 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1693 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); in asus_hides_smbus_lpc_ich6_suspend()
1706 val = readl(asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1709 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1736 u8 val = 0; in quirk_sis_96x_smbus()
1737 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1738 if (val & 0x10) { in quirk_sis_96x_smbus()
1740 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1760 #define SIS_DETECT_REGISTER 0x40
1770 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { in quirk_sis_503()
1795 int asus_hides_ac97 = 0; in asus_hides_ac97_lpc()
1805 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1806 if (val & 0xc0) { in asus_hides_ac97_lpc()
1807 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1808 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1809 if (val & 0xc0) in asus_hides_ac97_lpc()
1810 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1830 /* Only poke fn 0 */ in quirk_jmicron_ata()
1834 pci_read_config_dword(pdev, 0x40, &conf1); in quirk_jmicron_ata()
1835 pci_read_config_dword(pdev, 0x80, &conf5); in quirk_jmicron_ata()
1837 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1845 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ in quirk_jmicron_ata()
1856 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ in quirk_jmicron_ata()
1857 /* Set the class codes correctly and then direct IDE 0 */ in quirk_jmicron_ata()
1858 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ in quirk_jmicron_ata()
1863 conf1 |= 0x00C00000; /* Set 22, 23 */ in quirk_jmicron_ata()
1867 pci_write_config_dword(pdev, 0x40, conf1); in quirk_jmicron_ata()
1868 pci_write_config_dword(pdev, 0x80, conf5); in quirk_jmicron_ata()
1907 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, qu…
1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1916 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1924 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) in quirk_alder_ioapic()
1925 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1932 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1957 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch…
1978 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
2057 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
2089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
2098 return 0; in dmi_disable_ioapicreroute()
2168 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2171 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2190 case 0x3c28: /* Xeon E5 1600/2600/4600 */ in quirk_disable_intel_boot_interrupt()
2191 case 0x0e28: /* Xeon E5/E7 V2 */ in quirk_disable_intel_boot_interrupt()
2192 case 0x2f28: /* Xeon E5/E7 V3,V4 */ in quirk_disable_intel_boot_interrupt()
2193 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2194 case 0x2034: /* Xeon Scalable Family */ in quirk_disable_intel_boot_interrupt()
2217 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2233 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2235 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2241 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2245 #define BC_HT1000_FEATURE_REG 0x64
2246 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2247 #define BC_HT1000_MAP_IDX 0xC00
2248 #define BC_HT1000_MAP_DATA 0xC01
2262 for (irq = 0x10; irq < 0x10 + 32; irq++) { in quirk_disable_broadcom_boot_interrupt()
2264 outb(0x00, BC_HT1000_MAP_DATA); in quirk_disable_broadcom_boot_interrupt()
2282 #define AMD_813X_MISC 0x40
2283 #define AMD_813X_NOIOAMODE (1<<0)
2284 #define AMD_813X_REV_B1 0x12
2285 #define AMD_813X_REV_B2 0x13
2309 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2324 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
2339 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2341 if (r->start & 0x8) { in quirk_tc86c001_ide()
2343 resource_set_range(r, 0, SZ_16); in quirk_tc86c001_ide()
2354 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2364 for (bar = 0; bar <= 1; bar++) in quirk_plx_pci9050()
2365 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
2366 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
2371 resource_set_range(r, 0, SZ_256); in quirk_plx_pci9050()
2377 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2378 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2379 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2380 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2382 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2385 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2386 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2390 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2391 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2400 * The subdevice ID is of the form 0x00PS, where <P> is the number in quirk_netmos()
2407 dev->subsystem_device == 0x0299) in quirk_netmos()
2418 (dev->class & 0xff); in quirk_netmos()
2433 case 0x1029: in quirk_e100_interrupt()
2434 case 0x1030 ... 0x1034: in quirk_e100_interrupt()
2435 case 0x1038 ... 0x103E: in quirk_e100_interrupt()
2436 case 0x1050 ... 0x1057: in quirk_e100_interrupt()
2437 case 0x1059: in quirk_e100_interrupt()
2438 case 0x1064 ... 0x106B: in quirk_e100_interrupt()
2439 case 0x1091 ... 0x1095: in quirk_e100_interrupt()
2440 case 0x1209: in quirk_e100_interrupt()
2441 case 0x1229: in quirk_e100_interrupt()
2442 case 0x2449: in quirk_e100_interrupt()
2443 case 0x2459: in quirk_e100_interrupt()
2444 case 0x245D: in quirk_e100_interrupt()
2445 case 0x27DC: in quirk_e100_interrupt()
2460 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
2474 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
2481 if (cmd_hi == 0) { in quirk_e100_interrupt()
2499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1);
2527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1);
2528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1);
2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2569 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2571 if (en1k & 0x200) { in quirk_p64h2_1k_io()
2576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2587 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2588 if (!(b & 0x20)) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2589 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2604 * bus leading to USB2.0 packet loss. in quirk_via_cx700_pci_parking_caching()
2625 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2626 if (b & 0x40) { in quirk_via_cx700_pci_parking_caching()
2628 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2634 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2635 if (b != 0) { in quirk_via_cx700_pci_parking_caching()
2637 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2640 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2643 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2655 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2658 if (rev == 0x05719000) { in quirk_brcm_5719_limit_mrrs()
2678 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2680 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi);
2734 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2736 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2757 &flags) == 0) { in msi_ht_cap_enabled()
2761 return (flags & HT_MSI_FLAGS_ENABLE) != 0; in msi_ht_cap_enabled()
2767 return 0; in msi_ht_cap_enabled()
2791 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2811 &flags) == 0) { in ht_enable_msi_mapping()
2848 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2860 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2863 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2866 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2872 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2875 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2878 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2881 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2884 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2887 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2890 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2893 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2896 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2899 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2902 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2905 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2926 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2931 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2944 int found = 0; in ht_check_msi_mapping()
2954 &flags) == 0) { in ht_check_msi_mapping()
2974 int found = 0; in host_bridge_with_leaf()
2977 for (i = dev_no + 1; i < 0x20; i++) { in host_bridge_with_leaf()
2978 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2984 if (pos != 0) { in host_bridge_with_leaf()
3006 int end = 0; in is_end_of_ht_chain()
3032 int found = 0; in nv_ht_enable_msi_mapping()
3035 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
3036 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3041 if (pos != 0) { in nv_ht_enable_msi_mapping()
3075 &flags) == 0) { in ht_disable_msi_mapping()
3099 if (found == 0) in __nv_msi_ht_cap_quirk()
3106 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3107 PCI_DEVFN(0, 0)); in __nv_msi_ht_cap_quirk()
3114 if (pos != 0) { in __nv_msi_ht_cap_quirk()
3146 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
3170 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3177 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ in quirk_msi_intx_disable_qca_bug()
3178 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3258 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3293 * live on PCI function 0, which might be the CardBus controller or the
3310 * This must be done via function #0 in ricoh_mmc_fixup_rl5c476()
3315 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
3316 if (disable & 0x02) in ricoh_mmc_fixup_rl5c476()
3319 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
3320 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
3321 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
3322 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
3323 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
3324 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
3325 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
3341 * This must be done via function #0 in ricoh_mmc_fixup_r5c832()
3346 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize in ricoh_mmc_fixup_r5c832()
3350 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3352 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3353 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3354 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3355 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3359 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
3360 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
3361 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
3362 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
3363 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
3364 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
3369 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
3371 if (disable & 0x02) in ricoh_mmc_fixup_r5c832()
3374 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
3375 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
3376 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
3377 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
3392 #define VTUNCERRMSK_REG 0x1ac
3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3412 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3424 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3441 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3465 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
3476 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3522 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
3528 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
3534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3549 #define I915_DEIER_REG 0x4400c
3552 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3559 if (readl(regs + I915_DEIER_REG) != 0) { in disable_igfx_irq()
3562 writel(0, regs + I915_DEIER_REG); in disable_igfx_irq()
3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3581 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3621 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3623 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3694 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { in mellanox_check_broken_intx_masking()
3718 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); in mellanox_check_broken_intx_masking()
3727 fw_major = fw_maj_min & 0xffff; in mellanox_check_broken_intx_masking()
3729 fw_subminor = fw_sub_min & 0xffff; in mellanox_check_broken_intx_masking()
3757 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3775 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3904 acpi_execute_simple_method(SXFP, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3906 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3907 acpi_execute_simple_method(SXIO, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3908 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3932 return 0; in reset_intel_82599_sfp_virtfn()
3935 #define SOUTH_CHICKEN2 0xc2004
3936 #define PCH_PP_STATUS 0xc7200
3937 #define PCH_PP_CONTROL 0xc7204
3938 #define MSG_CTL 0x45010
3939 #define NSDE_PWR_STATE 0xd0100
3949 return 0; in reset_ivb_igd()
3951 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3955 iowrite32(0x00000002, mmio_base + MSG_CTL); in reset_ivb_igd()
3963 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); in reset_ivb_igd()
3965 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; in reset_ivb_igd()
3971 if ((val & 0xb0000000) == 0) in reset_ivb_igd()
3978 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); in reset_ivb_igd()
3981 return 0; in reset_ivb_igd()
3994 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3998 * If this is the "probe" phase, return 0 indicating that we can in reset_chelsio_generic_dev()
4002 return 0; in reset_chelsio_generic_dev()
4028 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) in reset_chelsio_generic_dev()
4043 return 0; in reset_chelsio_generic_dev()
4046 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
4047 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
4048 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
4070 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) in nvme_disable_and_flr()
4074 return 0; in nvme_disable_and_flr()
4076 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); in nvme_disable_and_flr()
4128 return 0; in nvme_disable_and_flr()
4147 return 0; in delay_250ms_after_flr()
4150 #define PCI_DEVICE_ID_HINIC_VF 0x375E
4151 #define HINIC_VF_FLR_TYPE 0x1000
4153 #define HINIC_VF_OP 0xE80
4165 return 0; in reset_hinic_vf_dev()
4167 bar = pci_iomap(pdev, 0, 0); in reset_hinic_vf_dev()
4190 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); in reset_hinic_vf_dev()
4210 return 0; in reset_hinic_vf_dev()
4220 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4221 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4222 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4223 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
4228 { 0 }
4253 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4254 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4260 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4265 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */
4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias);
4267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias);
4281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4330 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4331 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4342 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4350 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4351 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4352 .driver_data = PCI_DEVFN(1, 0) },
4353 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4354 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4355 .driver_data = PCI_DEVFN(1, 0) },
4356 { 0 }
4367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4390 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4392 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4394 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4396 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4406 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); in quirk_mic_x200_dma_alias()
4407 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); in quirk_mic_x200_dma_alias()
4408 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); in quirk_mic_x200_dma_alias()
4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4422 * All possible slot numbers (0x20) are used, since we are unable to tell
4429 const unsigned int num_pci_slots = 0x20; in quirk_pex_vca_alias()
4432 for (slot = 0; slot < num_pci_slots; slot++) in quirk_pex_vca_alias()
4433 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); in quirk_pex_vca_alias()
4435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4465 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4469 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4471 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4473 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4475 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4494 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4496 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4498 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4500 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4502 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4504 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4506 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4508 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4510 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4512 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4514 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4516 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4518 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4520 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4522 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4524 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4526 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4528 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4530 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4532 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4534 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4536 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4538 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4540 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4542 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4544 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4546 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4548 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4560 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4562 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4564 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4568 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4615 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4616 * 0x54xx so we use that one. in quirk_chelsio_T5_disable_root_port_attributes()
4618 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4633 * caller desires. Return 0 otherwise.
4639 return 0; in pci_acs_ctrl_enabled()
4678 status = acpi_get_table("IVRS", 0, &header); in pci_quirk_amd_sb_acs()
4703 case 0xa000 ... 0xa7ff: /* ThunderX1 */ in pci_quirk_cavium_acs_match()
4704 case 0xaf84: /* ThunderX2 */ in pci_quirk_cavium_acs_match()
4705 case 0xb884: /* ThunderX3 */ in pci_quirk_cavium_acs_match()
4757 case 0x0710 ... 0x071e: in pci_quirk_zhaoxin_pcie_ports_acs()
4758 case 0x0721: in pci_quirk_zhaoxin_pcie_ports_acs()
4759 case 0x0723 ... 0x0752: in pci_quirk_zhaoxin_pcie_ports_acs()
4775 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4776 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4778 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4779 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4781 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4782 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4784 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4785 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4787 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4788 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4790 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4791 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4793 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4795 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4796 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4798 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4809 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) in pci_quirk_intel_pch_acs_match()
4825 return pci_acs_ctrl_enabled(acs_flags, 0); in pci_quirk_intel_pch_acs()
4871 return acs_flags ? 0 : 1; in pci_quirk_al_acs()
4884 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4885 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4897 * 0xa290-0xa29f PCI Express Root port #{0-16}
4898 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4909 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4925 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ in pci_quirk_intel_spt_pch_acs_match()
4926 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ in pci_quirk_intel_spt_pch_acs_match()
4927 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ in pci_quirk_intel_spt_pch_acs_match()
5023 case 0x0100 ... 0x010F: /* EM */ in pci_quirk_wangxun_nic_acs()
5024 case 0x1001: case 0x2001: /* SP */ in pci_quirk_wangxun_nic_acs()
5025 case 0x5010: case 0x5025: case 0x5040: /* AML */ in pci_quirk_wangxun_nic_acs()
5026 case 0x5110: case 0x5125: case 0x5140: /* AML */ in pci_quirk_wangxun_nic_acs()
5039 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
5040 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
5041 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
5042 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
5043 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
5044 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
5045 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
5046 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
5047 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
5048 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
5049 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
5050 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
5051 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
5052 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
5053 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
5054 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
5055 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
5056 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
5057 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
5058 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
5059 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
5060 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
5061 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
5062 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
5063 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
5064 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
5065 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
5066 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
5067 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
5068 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
5069 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
5071 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
5072 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
5073 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
5074 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
5075 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
5076 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
5077 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
5079 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
5080 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
5081 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
5082 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
5083 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
5084 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
5085 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
5086 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
5088 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
5089 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
5090 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
5092 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
5093 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
5094 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
5095 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
5097 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
5098 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
5099 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
5100 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
5102 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
5103 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
5106 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
5107 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
5109 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs },
5111 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
5115 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5116 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5120 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
5121 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
5122 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
5124 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
5126 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
5127 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
5128 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
5129 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
5130 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
5131 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
5132 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
5133 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
5135 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
5136 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
5137 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
5138 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
5139 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs },
5140 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs },
5141 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs },
5142 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs },
5143 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
5145 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs },
5146 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs },
5147 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs },
5148 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs },
5149 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs },
5150 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs },
5151 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs },
5152 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs },
5153 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs },
5154 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs },
5156 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
5158 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
5159 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
5160 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
5163 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
5164 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
5165 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
5167 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
5168 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
5169 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
5171 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
5172 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
5173 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
5175 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
5176 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
5177 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
5179 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5180 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5181 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5183 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5184 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5185 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5187 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5188 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5189 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5191 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5192 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5193 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5198 { 0 }
5209 * 0: Device does not provide all the desired controls
5210 * >0: Device provides all the controls in @acs_flags
5229 if (ret >= 0) in pci_dev_specific_acs_enabled()
5238 #define INTEL_LPC_RCBA_REG 0xf0
5240 #define INTEL_LPC_RCBA_MASK 0xffffc000
5242 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5245 #define INTEL_BSPR_REG 0x1104
5252 #define INTEL_UPDCR_REG 0x1014
5253 /* 5:0 Peer Decode Enable bits */
5254 #define INTEL_UPDCR_REG_MASK 0x3f
5266 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5295 return 0; in pci_quirk_enable_intel_lpc_acs()
5299 #define INTEL_MPC_REG 0xd8
5335 return 0; in pci_quirk_enable_intel_pch_acs()
5344 return 0; in pci_quirk_enable_intel_pch_acs()
5374 return 0; in pci_quirk_enable_intel_spt_pch_acs()
5398 return 0; in pci_quirk_disable_intel_spt_pch_acs_redir()
5421 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_enable_acs()
5429 if (ret >= 0) in pci_dev_specific_enable_acs()
5442 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_disable_acs_redir()
5450 if (ret >= 0) in pci_dev_specific_disable_acs_redir()
5459 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5462 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5467 int pos, i = 0, ret; in quirk_intel_qat_vf_cap()
5483 * is not the expected incorrect 0x00. in quirk_intel_qat_vf_cap()
5490 * PCIe Capability Structure is expected to be at 0x50 and should in quirk_intel_qat_vf_cap()
5491 * terminate the list (Next Capability pointer is 0x00). Verify in quirk_intel_qat_vf_cap()
5497 pos = 0x50; in quirk_intel_qat_vf_cap()
5499 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { in quirk_intel_qat_vf_cap()
5526 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5528 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5539 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5544 * AMD Starship/Matisse HD Audio Controller 0x1487
5545 * AMD Starship USB 3.0 Host Controller 0x148c
5546 * AMD Matisse USB 3.0 Host Controller 0x149c
5547 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5548 * Intel 82579V Gigabit Ethernet Controller 0x1503
5555 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5556 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5557 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5558 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr);
5563 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
5566 if (dev->revision == 0x1) in quirk_no_flr_snet()
5569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags);
5584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5587 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5588 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5589 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5590 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5596 pdev->ats_cap = 0; in quirk_no_ats()
5606 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5607 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5608 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5609 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5610 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5611 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5645 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5710 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_hda()
5725 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb()
5738 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5741 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb_typec_ucsi()
5763 /* Bit 25 at offset 0x488 enables the HDA controller */ in quirk_nvidia_hda()
5764 pci_read_config_dword(gpu, 0x488, &val); in quirk_nvidia_hda()
5769 pci_write_config_dword(gpu, 0x488, val | BIT(25)); in quirk_nvidia_hda()
5782 * completions for config read requests even though PCIe r4.0, sec
5795 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5808 u16 ctrl = 0; in pci_idt_bus_quirk()
5826 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); in pci_idt_bus_quirk()
5856 mmio = pci_iomap(pdev, 0, 0); in quirk_switchtec_ntb_dma_alias()
5874 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { in quirk_switchtec_ntb_dma_alias()
5876 u32 table_sz = 0; in quirk_switchtec_ntb_dma_alias()
5888 pci_warn(pdev, "Partition %d table_sz 0\n", pp); in quirk_switchtec_ntb_dma_alias()
5899 for (te = 0; te < table_sz; te++) { in quirk_switchtec_ntb_dma_alias()
5904 devfn = (rid_entry >> 1) & 0xFF; in quirk_switchtec_ntb_dma_alias()
5919 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5920 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5921 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5922 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5923 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5924 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5925 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5926 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5927 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5928 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5929 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5930 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5931 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5932 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5933 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5934 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5935 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5936 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5937 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5938 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5939 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5940 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5941 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5942 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5943 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5944 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5945 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5946 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5947 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5948 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5949 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5950 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5951 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5952 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5953 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5954 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5955 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5956 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5957 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5958 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5959 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5960 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5961 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5962 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5963 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5964 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5965 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5966 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5967 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5968 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5969 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5970 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5971 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5972 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5973 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5974 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5975 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5976 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */
5977 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */
5978 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */
5979 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */
5980 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */
5981 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */
5982 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */
5983 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */
5984 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */
5985 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */
5986 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */
5987 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */
5988 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */
5989 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */
5990 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */
5991 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */
5992 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */
5993 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */
5994 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */
5995 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */
5996 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */
5997 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */
5998 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */
5999 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */
6000 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */
6001 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */
6002 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */
6003 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */
6004 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */
6005 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */
6006 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */
6007 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */
6008 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */
6009 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */
6010 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */
6011 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */
6016 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */
6017 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */
6018 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */
6019 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */
6020 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */
6021 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */
6034 pci_add_dma_alias(pdev, 0, 256); in quirk_plx_ntb_dma_alias()
6036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
6037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
6061 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6072 map = pci_iomap(pdev, 0, 0x23000); in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6082 if (ioread32(map + 0x2240c) & 0x2) { in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6085 if (ret < 0) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6093 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
6106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
6109 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
6125 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
6128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
6134 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
6146 #define PI7C9X2Gxxx_MODE_REG 0x74
6147 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
6179 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
6181 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
6183 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
6185 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
6187 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
6189 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
6196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
6203 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
6204 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
6205 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
6206 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
6222 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", in aspm_l1_acceptable_latency()
6226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
6227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
6228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
6229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
6230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
6231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
6232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
6233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
6234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
6235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
6236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
6237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
6238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
6239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
6240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
6241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
6242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
6243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
6244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
6245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
6246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
6247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
6248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
6249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6272 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { in dpc_log_size()
6278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size);
6295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size);
6296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
6307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
6308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
6323 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);
6341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);
6342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);