Lines Matching +full:pm +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/pm.h>
50 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
66 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
74 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); in pci_configure_aspm_l1ss()
85 struct pci_dev *parent = pdev->bus->self; in pci_save_aspm_l1ss_state()
97 if (!pdev->l1ss || !parent->l1ss) in pci_save_aspm_l1ss_state()
108 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
109 pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cap++); in pci_save_aspm_l1ss_state()
110 pci_read_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cap++); in pci_save_aspm_l1ss_state()
120 cap = &save_state->cap.data[0]; in pci_save_aspm_l1ss_state()
121 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, cap++); in pci_save_aspm_l1ss_state()
122 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, cap++); in pci_save_aspm_l1ss_state()
128 struct pci_dev *parent = pdev->bus->self; in pci_restore_aspm_l1ss_state()
141 if (!pdev->l1ss || !parent->l1ss) in pci_restore_aspm_l1ss_state()
149 cap = &cl_save_state->cap.data[0]; in pci_restore_aspm_l1ss_state()
152 cap = &pl_save_state->cap.data[0]; in pci_restore_aspm_l1ss_state()
171 pci_clear_and_set_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
173 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
187 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2); in pci_restore_aspm_l1ss_state()
188 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2); in pci_restore_aspm_l1ss_state()
189 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1); in pci_restore_aspm_l1ss_state()
190 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1); in pci_restore_aspm_l1ss_state()
194 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
196 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, in pci_restore_aspm_l1ss_state()
243 /* Clock PM state */
244 u32 clkpm_capable:1; /* Clock PM capable? */
245 u32 clkpm_enabled:1; /* Current Clock PM state */
246 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
247 u32 clkpm_disable:1; /* Clock PM disabled */
278 * The L1 PM substate capability is only implemented in function 0 in a
285 list_for_each_entry(child, &linkbus->devices, bus_list) in pci_function_0()
286 if (PCI_FUNC(child->devfn) == 0) in pci_function_0()
295 /* Disable ASPM and Clock PM */ in policy_to_aspm_state()
304 return link->aspm_default; in policy_to_aspm_state()
313 /* Disable ASPM and Clock PM */ in policy_to_clkpm_state()
317 /* Enable Clock PM */ in policy_to_clkpm_state()
320 return link->clkpm_default; in policy_to_clkpm_state()
345 cap = (u16 *)&save_state->cap.data[0]; in pci_update_aspm_saved_state()
352 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_set_clkpm_nocheck()
355 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_set_clkpm_nocheck()
361 link->clkpm_enabled = !!enable; in pcie_set_clkpm_nocheck()
367 * Don't enable Clock PM if the link is not Clock PM capable in pcie_set_clkpm()
368 * or Clock PM is disabled in pcie_set_clkpm()
370 if (!link->clkpm_capable || link->clkpm_disable) in pcie_set_clkpm()
373 if (link->clkpm_enabled == enable) in pcie_set_clkpm()
384 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_clkpm_cap_init()
387 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_clkpm_cap_init()
398 link->clkpm_enabled = enabled; in pcie_clkpm_cap_init()
399 link->clkpm_default = enabled; in pcie_clkpm_cap_init()
400 link->clkpm_capable = capable; in pcie_clkpm_cap_init()
401 link->clkpm_disable = blacklist ? 1 : 0; in pcie_clkpm_cap_init()
413 struct pci_dev *child, *parent = link->pdev; in pcie_aspm_configure_common_clock()
414 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_configure_common_clock()
419 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); in pcie_aspm_configure_common_clock()
438 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
453 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_configure_common_clock()
455 child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC; in pcie_aspm_configure_common_clock()
464 if (pcie_retrain_link(link->pdev, true)) { in pcie_aspm_configure_common_clock()
468 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_aspm_configure_common_clock()
471 child_old_ccc[PCI_FUNC(child->devfn)]); in pcie_aspm_configure_common_clock()
529 * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
541 * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max in encode_l12_threshold()
577 if ((endpoint->current_state != PCI_D0) && in pcie_aspm_check_latency()
578 (endpoint->current_state != PCI_UNKNOWN)) in pcie_aspm_check_latency()
581 link = endpoint->bus->self->link_state; in pcie_aspm_check_latency()
584 encoding = FIELD_GET(PCI_EXP_DEVCAP_L0S, endpoint->devcap); in pcie_aspm_check_latency()
588 encoding = FIELD_GET(PCI_EXP_DEVCAP_L1, endpoint->devcap); in pcie_aspm_check_latency()
592 struct pci_dev *dev = pci_function_0(link->pdev->subordinate); in pcie_aspm_check_latency()
595 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP, in pcie_aspm_check_latency()
605 if ((link->aspm_capable & PCIE_LINK_STATE_L0S_UP) && in pcie_aspm_check_latency()
607 link->aspm_capable &= ~PCIE_LINK_STATE_L0S_UP; in pcie_aspm_check_latency()
610 if ((link->aspm_capable & PCIE_LINK_STATE_L0S_DW) && in pcie_aspm_check_latency()
612 link->aspm_capable &= ~PCIE_LINK_STATE_L0S_DW; in pcie_aspm_check_latency()
627 if ((link->aspm_capable & PCIE_LINK_STATE_L1) && in pcie_aspm_check_latency()
629 link->aspm_capable &= ~PCIE_LINK_STATE_L1; in pcie_aspm_check_latency()
632 link = link->parent; in pcie_aspm_check_latency()
636 /* Calculate L1.2 PM substate timing parameters */
640 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l12_info()
675 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and in aspm_calc_l12_info()
676 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at in aspm_calc_l12_info()
686 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1); in aspm_calc_l12_info()
687 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2); in aspm_calc_l12_info()
688 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1); in aspm_calc_l12_info()
689 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2); in aspm_calc_l12_info()
701 child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
704 parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
709 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
710 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2); in aspm_calc_l12_info()
713 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
717 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
721 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_calc_l12_info()
728 parent->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l12_info()
731 child->l1ss + PCI_L1SS_CTL1, 0, in aspm_calc_l12_info()
738 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_l1ss_init()
742 if (!parent->l1ss || !child->l1ss) in aspm_l1ss_init()
746 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
748 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP, in aspm_l1ss_init()
761 if (!child->ltr_path) in aspm_l1ss_init()
765 link->aspm_support |= PCIE_LINK_STATE_L1_1; in aspm_l1ss_init()
767 link->aspm_support |= PCIE_LINK_STATE_L1_2; in aspm_l1ss_init()
769 link->aspm_support |= PCIE_LINK_STATE_L1_1_PCIPM; in aspm_l1ss_init()
771 link->aspm_support |= PCIE_LINK_STATE_L1_2_PCIPM; in aspm_l1ss_init()
774 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
777 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in aspm_l1ss_init()
781 link->aspm_enabled |= PCIE_LINK_STATE_L1_1; in aspm_l1ss_init()
783 link->aspm_enabled |= PCIE_LINK_STATE_L1_2; in aspm_l1ss_init()
785 link->aspm_enabled |= PCIE_LINK_STATE_L1_1_PCIPM; in aspm_l1ss_init()
787 link->aspm_enabled |= PCIE_LINK_STATE_L1_2_PCIPM; in aspm_l1ss_init()
789 if (link->aspm_support & PCIE_LINK_STATE_L1_2_MASK) in aspm_l1ss_init()
797 struct pci_dev *pdev = link->downstream; in pcie_aspm_override_default_link_state()
802 if (link->aspm_support & PCIE_LINK_STATE_L0S) in pcie_aspm_override_default_link_state()
803 link->aspm_default |= PCIE_LINK_STATE_L0S; in pcie_aspm_override_default_link_state()
804 if (link->aspm_support & PCIE_LINK_STATE_L1) in pcie_aspm_override_default_link_state()
805 link->aspm_default |= PCIE_LINK_STATE_L1; in pcie_aspm_override_default_link_state()
806 override = link->aspm_default & ~link->aspm_enabled; in pcie_aspm_override_default_link_state()
816 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init()
818 struct pci_bus *linkbus = parent->subordinate; in pcie_aspm_cap_init()
822 link->aspm_enabled = PCIE_LINK_STATE_ASPM_ALL; in pcie_aspm_cap_init()
823 link->aspm_disable = PCIE_LINK_STATE_ASPM_ALL; in pcie_aspm_cap_init()
831 if (!(parent->aspm_l0s_support && child->aspm_l0s_support) && in pcie_aspm_cap_init()
832 !(parent->aspm_l1_support && child->aspm_l1_support)) in pcie_aspm_cap_init()
839 * Re-read upstream/downstream components' register state after in pcie_aspm_cap_init()
841 * read-only Link Capabilities may change depending on common clock in pcie_aspm_cap_init()
863 if (parent->aspm_l0s_support && child->aspm_l0s_support) in pcie_aspm_cap_init()
864 link->aspm_support |= PCIE_LINK_STATE_L0S; in pcie_aspm_cap_init()
867 link->aspm_enabled |= PCIE_LINK_STATE_L0S_UP; in pcie_aspm_cap_init()
869 link->aspm_enabled |= PCIE_LINK_STATE_L0S_DW; in pcie_aspm_cap_init()
872 if (parent->aspm_l1_support && child->aspm_l1_support) in pcie_aspm_cap_init()
873 link->aspm_support |= PCIE_LINK_STATE_L1; in pcie_aspm_cap_init()
876 link->aspm_enabled |= PCIE_LINK_STATE_L1; in pcie_aspm_cap_init()
888 link->aspm_default = link->aspm_enabled; in pcie_aspm_cap_init()
893 link->aspm_capable = link->aspm_support; in pcie_aspm_cap_init()
896 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_aspm_cap_init()
909 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss()
921 * PCIe r6.2, sec 5.5.4, rules for enabling L1 PM Substates: in pcie_config_aspm_l1ss()
922 * - Clear L1.x enable bits at child first, then at parent in pcie_config_aspm_l1ss()
923 * - Set L1.x enable bits at parent first, then at child in pcie_config_aspm_l1ss()
924 * - ASPM/PCIPM L1.2 must be disabled while programming timing in pcie_config_aspm_l1ss()
929 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
931 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
935 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
937 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1, in pcie_config_aspm_l1ss()
950 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link()
951 struct pci_bus *linkbus = parent->subordinate; in pcie_config_aspm_link()
954 state &= (link->aspm_capable & ~link->aspm_disable); in pcie_config_aspm_link()
960 /* Spec says both ports must be in D0 before enabling PCI PM substates*/ in pcie_config_aspm_link()
961 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { in pcie_config_aspm_link()
963 state |= (link->aspm_enabled & PCIE_LINK_STATE_L1_SS_PCIPM); in pcie_config_aspm_link()
967 if (link->aspm_enabled == state) in pcie_config_aspm_link()
981 * bits for ASPM L1 PM Substates must be done while ASPM L1 is in pcie_config_aspm_link()
991 * value for all functions of a multi-function device. in pcie_config_aspm_link()
993 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
997 if (link->aspm_capable & PCIE_LINK_STATE_L1SS) in pcie_config_aspm_link()
1001 list_for_each_entry(child, &linkbus->devices, bus_list) in pcie_config_aspm_link()
1004 link->aspm_enabled = state; in pcie_config_aspm_link()
1007 pci_save_aspm_l1ss_state(link->downstream); in pcie_config_aspm_link()
1008 pci_update_aspm_saved_state(link->downstream); in pcie_config_aspm_link()
1017 link = link->parent; in pcie_config_aspm_path()
1023 link->pdev->link_state = NULL; in free_link_state()
1036 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { in pcie_aspm_sanity_check()
1038 return -EINVAL; in pcie_aspm_sanity_check()
1043 * pre-1.1 device in pcie_aspm_sanity_check()
1050 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use in pcie_aspm_sanity_check()
1055 …pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\… in pcie_aspm_sanity_check()
1056 return -EINVAL; in pcie_aspm_sanity_check()
1070 INIT_LIST_HEAD(&link->sibling); in alloc_pcie_link_state()
1071 link->pdev = pdev; in alloc_pcie_link_state()
1072 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
1075 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe in alloc_pcie_link_state()
1083 !pdev->bus->parent->self) { in alloc_pcie_link_state()
1084 link->root = link; in alloc_pcie_link_state()
1088 parent = pdev->bus->parent->self->link_state; in alloc_pcie_link_state()
1094 link->parent = parent; in alloc_pcie_link_state()
1095 link->root = link->parent->root; in alloc_pcie_link_state()
1098 list_add(&link->sibling, &link_list); in alloc_pcie_link_state()
1099 pdev->link_state = link; in alloc_pcie_link_state()
1107 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) in pcie_aspm_update_sysfs_visibility()
1108 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group); in pcie_aspm_update_sysfs_visibility()
1124 if (pdev->link_state) in pcie_aspm_init_link_state()
1137 pdev->bus->self) in pcie_aspm_init_link_state()
1141 if (list_empty(&pdev->subordinate->devices)) in pcie_aspm_init_link_state()
1155 /* Setup initial Clock PM state */ in pcie_aspm_init_link_state()
1186 if (bridge && bridge->ltr_path) { in pci_bridge_reconfigure_ltr()
1189 pci_dbg(bridge, "re-enabling LTR\n"); in pci_bridge_reconfigure_ltr()
1198 struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus); in pci_configure_ltr()
1212 pdev->ltr_path = 1; in pci_configure_ltr()
1217 if (bridge && bridge->ltr_path) in pci_configure_ltr()
1218 pdev->ltr_path = 1; in pci_configure_ltr()
1223 if (!host->native_ltr) in pci_configure_ltr()
1234 pdev->ltr_path = 1; in pci_configure_ltr()
1239 * If we're configuring a hot-added device, LTR was likely in pci_configure_ltr()
1240 * disabled in the upstream bridge, so re-enable it before enabling in pci_configure_ltr()
1244 if (bridge && bridge->ltr_path) { in pci_configure_ltr()
1248 pdev->ltr_path = 1; in pci_configure_ltr()
1256 BUG_ON(root->parent); in pcie_update_aspm_capable()
1258 if (link->root != root) in pcie_update_aspm_capable()
1260 link->aspm_capable = link->aspm_support; in pcie_update_aspm_capable()
1264 struct pci_bus *linkbus = link->pdev->subordinate; in pcie_update_aspm_capable()
1265 if (link->root != root) in pcie_update_aspm_capable()
1267 list_for_each_entry(child, &linkbus->devices, bus_list) { in pcie_update_aspm_capable()
1279 struct pci_dev *parent = pdev->bus->self; in pcie_aspm_exit_link_state()
1282 if (!parent || !parent->link_state) in pcie_aspm_exit_link_state()
1288 link = parent->link_state; in pcie_aspm_exit_link_state()
1289 root = link->root; in pcie_aspm_exit_link_state()
1290 parent_link = link->parent; in pcie_aspm_exit_link_state()
1294 * link->downstream) being removed. in pcie_aspm_exit_link_state()
1300 if (pdev != link->downstream) in pcie_aspm_exit_link_state()
1304 list_del(&link->sibling); in pcie_aspm_exit_link_state()
1324 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_pm_state_change()
1329 * Devices changed PM state, we should recheck if latency in pcie_aspm_pm_state_change()
1335 pcie_update_aspm_capable(link->root); in pcie_aspm_pm_state_change()
1344 struct pcie_link_state *link = pdev->link_state; in pcie_aspm_powersave_config_link()
1372 return bridge->link_state; in pcie_aspm_get_link()
1379 /* L1 PM substates require L1 */ in pci_calc_aspm_disable_mask()
1390 /* L1 PM substates require L1 */ in pci_calc_aspm_enable_mask()
1402 return -EINVAL; in __pci_disable_link_state()
1413 return -EPERM; in __pci_disable_link_state()
1419 link->aspm_disable |= pci_calc_aspm_disable_mask(state); in __pci_disable_link_state()
1423 link->clkpm_disable = 1; in __pci_disable_link_state()
1441 * pci_disable_link_state - Disable device's link state, so the link will
1460 return -EINVAL; in __pci_enable_link_state()
1469 return -EPERM; in __pci_enable_link_state()
1475 link->aspm_default = pci_calc_aspm_enable_mask(state); in __pci_enable_link_state()
1478 link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0; in __pci_enable_link_state()
1488 * pci_enable_link_state - Clear and set the default device link state so that
1494 * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1507 * pci_enable_link_state_locked - Clear and set the default device link state
1513 * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1532 pdev->aspm_l0s_support = 0; in pcie_aspm_remove_cap()
1534 pdev->aspm_l1_support = 0; in pcie_aspm_remove_cap()
1549 return -EPERM; in pcie_aspm_set_policy()
1584 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1599 return link->aspm_enabled; in pcie_aspm_enabled()
1610 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0); in aspm_attr_show_common()
1622 return -EINVAL; in aspm_attr_store_common()
1628 link->aspm_disable &= ~state; in aspm_attr_store_common()
1631 link->aspm_disable &= ~PCIE_LINK_STATE_L1; in aspm_attr_store_common()
1633 link->aspm_disable |= state; in aspm_attr_store_common()
1635 link->aspm_disable |= PCIE_LINK_STATE_L1SS; in aspm_attr_store_common()
1669 return sysfs_emit(buf, "%d\n", link->clkpm_enabled); in ASPM_ATTR()
1681 return -EINVAL; in clkpm_store()
1686 link->clkpm_disable = !state_enable; in clkpm_store()
1733 return link->clkpm_capable ? a->mode : 0; in aspm_ctrl_attrs_are_visible()
1735 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0; in aspm_ctrl_attrs_are_visible()