1 /* SPDX-License-Identifier: GPL-2.0 */
37  * "T_PERST-CLK".
42  * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
50  * - "With a Downstream Port that does not support Link speeds greater
55  * - "With a Downstream Port that supports Link speeds greater than
102  * PCI_FIND_NEXT_CAP - Find a PCI standard capability
109  * Implements TTL (time-to-live) protection against infinite loops.
122 	while (__ttl--) {						\
145  * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability
164 	__ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;	\
165 	while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) {		\
259 	pm_wakeup_event(&dev->dev, 100);  in pci_wakeup_event()
263  * pci_bar_index_is_valid - Check whether a BAR index is within valid range
280 	return !!(pci_dev->subordinate);  in pci_has_subordinate()
289 	return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;  in pci_power_manageable()
352 	if (dev->bus->self)  in pci_no_d1d2()
353 		parent_dstates = dev->bus->self->no_d1d2;  in pci_no_d1d2()
354 	return (dev->no_d1d2 || parent_dstates);  in pci_no_d1d2()
383  * pci_match_one_device - Tell if a PCI device structure has a matching
393 	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&  in pci_match_one_device()
394 	    (id->device == PCI_ANY_ID || id->device == dev->device) &&  in pci_match_one_device()
395 	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&  in pci_match_one_device()
396 	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&  in pci_match_one_device()
397 	    !((id->class ^ dev->class) & id->class_mask))  in pci_match_one_device()
417 	pci_bar_mem32,		/* A 32-bit memory BAR */
418 	pci_bar_mem64,		/* A 64-bit memory BAR */
455  * pci_resource_num - Reverse lookup resource number from device resources
468 	int resno = res - &dev->resource[0];  in pci_resource_num()
548 	return -EINVAL;  in pcie_dev_speed_mbps()
558 	bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];  in __pcie_update_link_speed()
559 	bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0;  in __pcie_update_link_speed()
567 	u32		cap;		/* SR-IOV Capabilities */
568 	u16		ctrl;		/* SR-IOV Control */
617  * pci_dev_set_io_state - Set the new error state if possible.
634 		xchg(&dev->error_state, pci_channel_io_perm_failure);  in pci_dev_set_io_state()
637 		old = cmpxchg(&dev->error_state, pci_channel_io_normal,  in pci_dev_set_io_state()
641 		old = cmpxchg(&dev->error_state, pci_channel_io_frozen,  in pci_dev_set_io_state()
670 	set_bit(PCI_DEV_ADDED, &dev->priv_flags);  in pci_dev_assign_added()
676 	return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags);  in pci_dev_test_and_clear_added()
681 	return test_bit(PCI_DEV_ADDED, &dev->priv_flags);  in pci_dev_is_added()
686 	return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags);  in pci_dev_test_and_set_removed()
691 	set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags);  in pci_dev_allow_binding()
696 	return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags);  in pci_dev_binding_disallowed()
816 	if (!dev->is_physfn)  in pci_iov_vf_rebar_cap()
819 	return dev->sriov->vf_rebar_cap;  in pci_iov_vf_rebar_cap()
831 	return resno - PCI_IOV_RESOURCES;  in pci_resource_num_to_vf_bar()
838 	return -ENODEV;  in pci_iov_init()
870 	return -ENODEV;  in pci_resource_num_from_vf_bar()
875 	return -ENODEV;  in pci_resource_num_to_vf_bar()
914 	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)  in pci_resource_alignment()
929 	return -ENOTTY;  in pci_dev_specific_acs_enabled()
933 	return -ENOTTY;  in pci_dev_specific_enable_acs()
937 	return -ENOTTY;  in pci_dev_specific_disable_acs_redir()
941 	return -ENOTTY;  in pcie_failed_link_retrain()
950 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
953 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */
1007 	return -ENOTTY;  in pci_dev_specific_reset()
1018 	return -ENODEV;  in acpi_get_rc_resources()
1044 	u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES];
1068 	return -1;  in of_get_pci_domain_nr()
1074 	return -EINVAL;  in of_pci_get_max_link_speed()
1113 	presets->eq_presets_8gts[0] = PCI_EQ_RESV;  in of_pci_get_equalization_presets()
1114 	for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++)  in of_pci_get_equalization_presets()
1115 		presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV;  in of_pci_get_equalization_presets()
1156 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }  in pci_aer_clear_status()
1157 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }  in pci_aer_raw_clear_status()
1183 	return -ENOTTY;  in pci_dev_acpi_reset()
1188 	return -ENODEV;  in pci_acpi_program_hp_params()
1200 	return -ENODEV;  in acpi_pci_set_power_state()
1209 	return -ENODEV;  in acpi_pci_wakeup()
1236 	return -ENODEV;  in mid_pci_set_power_state()
1249 	return -ENODEV;  in pci_msix_write_tph_tag()
1257  * Section 3.2.2.3.2, Figure 3-2, p. 50.
1285  * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
1287  * are used for specifying additional 4 high bits of PCI Express register.