Lines Matching +full:power +full:- +full:up +full:- +full:delay +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
13 #include <linux/delay.h>
82 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
86 /* Use a 20% upper bound, 1ms minimum */ in pci_dev_d3_sleep()
95 return dev->reset_methods[0] != 0; in pci_reset_supported()
114 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
125 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
142 * measured in 32-bit words, not bytes.
148 * If we set up a device for bus mastering, we need to check the latency
184 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
195 max = bus->busn_res.end; in pci_bus_max_busnr()
196 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
206 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
218 return -EIO; in pci_status_get_and_clear_errors()
232 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
233 resource_size_t start = res->start; in __pci_ioremap_resource()
239 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
264 * pci_dev_str_match_path - test if a path string matches a device
275 * A path for a device can be obtained using 'lspci -t'. Using a path
292 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
294 return -ENOMEM; in pci_dev_str_match_path()
302 ret = -EINVAL; in pci_dev_str_match_path()
306 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
332 ret = -EINVAL; in pci_dev_str_match_path()
337 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
338 bus == dev->bus->number && in pci_dev_str_match_path()
339 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
347 * pci_dev_str_match - test if a string matches a device
364 * through the use of 'lspci -t'.
369 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
391 return -EINVAL; in pci_dev_str_match()
399 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
400 (!device || device == dev->device) && in pci_dev_str_match()
402 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
404 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
434 while ((*ttl)--) { in __pci_find_next_cap_ttl()
460 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
486 * pci_find_capability - query for devices' capabilities
495 * %PCI_CAP_ID_PM Power Management
501 * %PCI_CAP_ID_PCIX PCI-X
508 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
510 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
517 * pci_bus_find_capability - query for devices' capabilities
523 * pci_dev structure set up yet.
544 * pci_find_next_ext_capability - Find an extended capability
552 * vendor-specific capability, and this provides a way to find them all.
561 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
563 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
579 while (ttl-- > 0) { in pci_find_next_ext_capability()
596 * pci_find_ext_capability - Find an extended capability
607 * %PCI_EXT_CAP_ID_PWR Power Budgeting
616 * pci_get_dsn - Read and return the 8-byte Device Serial Number
619 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
659 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
669 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
678 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
697 * pci_find_ht_capability - query a device's HyperTransport capabilities
711 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
720 * pci_find_vsec_capability - Find a vendor-specific extended capability
723 * @cap: Vendor-specific capability ID
735 if (vendor != dev->vendor) in pci_find_vsec_capability()
753 * pci_find_dvsec_capability - Find DVSEC for vendor
756 * @dvsec: Designated Vendor-specific capability ID
785 * pci_find_parent_resource - return resource region of parent bus of given
796 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
808 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
809 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
814 * be both a positively-decoded aperture and a in pci_find_parent_resource()
815 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
816 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
828 * pci_find_resource - Return matching PCI device resource
841 struct resource *r = &dev->resource[i]; in pci_find_resource()
843 if (r->start && resource_contains(r, res)) in pci_find_resource()
852 * pci_resource_name - Return the name of the PCI resource
901 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS && in pci_resource_name()
912 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
927 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
940 * pci_request_acs - ask for ACS to be enabled if supported
973 end = delimit - p - 1; in __pci_config_acs()
975 while (end > -1) { in __pci_config_acs()
979 end--; in __pci_config_acs()
984 end--; in __pci_config_acs()
987 end--; in __pci_config_acs()
1032 caps->ctrl = (caps->ctrl & ~mask) | (caps->fw_ctrl & mask); in __pci_config_acs()
1033 caps->ctrl |= flags; in __pci_config_acs()
1035 pci_info(dev, "Configured ACS to %#06x\n", caps->ctrl); in __pci_config_acs()
1039 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1046 caps->ctrl |= (caps->cap & PCI_ACS_SV); in pci_std_enable_acs()
1049 caps->ctrl |= (caps->cap & PCI_ACS_RR); in pci_std_enable_acs()
1052 caps->ctrl |= (caps->cap & PCI_ACS_CR); in pci_std_enable_acs()
1055 caps->ctrl |= (caps->cap & PCI_ACS_UF); in pci_std_enable_acs()
1058 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
1059 caps->ctrl |= (caps->cap & PCI_ACS_TB); in pci_std_enable_acs()
1063 * pci_enable_acs - enable ACS if hardware support it
1078 pos = dev->acs_cap; in pci_enable_acs()
1102 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1180 * pci_update_current_state - Read power state of given device and cache it
1184 * The power state is read from the PMCSR register, which however is
1187 * reports an incorrect state or the device isn't power manageable by the
1194 dev->current_state = PCI_D3cold; in pci_update_current_state()
1195 } else if (dev->pm_cap) { in pci_update_current_state()
1198 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1200 dev->current_state = PCI_D3cold; in pci_update_current_state()
1203 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1205 dev->current_state = state; in pci_update_current_state()
1210 * pci_refresh_power_state - Refresh the given device's power state data
1213 * Ask the platform to refresh the devices power state information and invoke
1214 * pci_update_current_state() to update its current PCI power state.
1219 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1223 * pci_platform_power_transition - Use platform to change device power state
1234 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1235 dev->current_state = PCI_D0; in pci_platform_power_transition()
1243 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1248 * pci_resume_bus - Walk given bus and runtime resume devices on it
1259 int delay = 1; in pci_dev_wait() local
1280 * Vendor ID until we get non-RRS status. in pci_dev_wait()
1287 * ID for VFs and non-existent devices also returns ~0, so read the in pci_dev_wait()
1295 return -ENOTTY; in pci_dev_wait()
1298 if (root && root->config_rrs_sv) { in pci_dev_wait()
1308 if (delay > timeout) { in pci_dev_wait()
1309 pci_warn(dev, "not ready %dms after %s; giving up\n", in pci_dev_wait()
1310 delay - 1, reset_type); in pci_dev_wait()
1311 return -ENOTTY; in pci_dev_wait()
1314 if (delay > PCI_RESET_WAIT) { in pci_dev_wait()
1318 delay = 1; in pci_dev_wait()
1323 delay - 1, reset_type); in pci_dev_wait()
1326 msleep(delay); in pci_dev_wait()
1327 delay *= 2; in pci_dev_wait()
1330 if (delay > PCI_RESET_WAIT) in pci_dev_wait()
1331 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1334 pci_dbg(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1341 * pci_power_up - Put the given device into D0
1342 * @dev: PCI device to power up
1348 * lacks a Power Management Capability, even if the platform was able to
1349 * put the device in D0 via non-PCI means.
1359 if (!dev->pm_cap) { in pci_power_up()
1362 dev->current_state = PCI_D0; in pci_power_up()
1364 dev->current_state = state; in pci_power_up()
1366 return -EIO; in pci_power_up()
1369 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1371 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n", in pci_power_up()
1372 pci_power_name(dev->current_state)); in pci_power_up()
1373 dev->current_state = PCI_D3cold; in pci_power_up()
1374 return -EIO; in pci_power_up()
1379 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1389 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1398 dev->current_state = PCI_D0; in pci_power_up()
1406 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1407 * @dev: PCI device to power up
1412 * reconfigure ASPM in accordance with the new power state.
1414 * If pci_restore_state() is going to be called right after a power state change
1425 if (dev->current_state == PCI_D0) in pci_set_full_power_state()
1431 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1432 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1433 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1434 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n", in pci_set_full_power_state()
1435 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1438 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT in pci_set_full_power_state()
1453 if (dev->bus->self) in pci_set_full_power_state()
1454 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_full_power_state()
1460 * __pci_dev_set_current_state - Set current state of a PCI device
1468 dev->current_state = state; in __pci_dev_set_current_state()
1473 * pci_bus_set_current_state - Walk given bus and set current state of devices
1495 * pci_set_low_power_state - Put a PCI device into a low-power state.
1497 * @state: PCI power state (D1, D2, D3hot) to put the device into.
1500 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1503 * -EINVAL if the requested state is invalid.
1504 * -EIO if device does not support PCI PM or its PM capabilities register has a
1507 * 0 if device's power state has been successfully changed.
1513 if (!dev->pm_cap) in pci_set_low_power_state()
1514 return -EIO; in pci_set_low_power_state()
1518 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1522 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1523 pci_dbg(dev, "Invalid power transition (from %s to %s)\n", in pci_set_low_power_state()
1524 pci_power_name(dev->current_state), in pci_set_low_power_state()
1526 return -EINVAL; in pci_set_low_power_state()
1530 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1531 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1532 return -EIO; in pci_set_low_power_state()
1534 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1536 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n", in pci_set_low_power_state()
1537 pci_power_name(dev->current_state), in pci_set_low_power_state()
1539 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1540 return -EIO; in pci_set_low_power_state()
1547 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1549 /* Mandatory power management transition delays; see PCI PM 1.2. */ in pci_set_low_power_state()
1555 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1556 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1557 if (dev->current_state != state) in pci_set_low_power_state()
1558 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n", in pci_set_low_power_state()
1559 pci_power_name(dev->current_state), in pci_set_low_power_state()
1562 if (dev->bus->self) in pci_set_low_power_state()
1563 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_low_power_state()
1588 if (dev->current_state == state) in __pci_set_power_state()
1598 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in __pci_set_power_state()
1611 /* Powering off a bridge may power off the whole hierarchy */ in __pci_set_power_state()
1612 if (dev->current_state == PCI_D3cold) in __pci_set_power_state()
1613 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked); in __pci_set_power_state()
1625 * pci_set_power_state - Set the power state of a PCI device
1627 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1629 * Transition a device to a new power state, using the platform firmware and/or
1633 * -EINVAL if the requested state is invalid.
1634 * -EIO if device does not support PCI PM or its PM capabilities register has a
1639 * 0 if device's power state has been successfully changed.
1662 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1663 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1691 return -ENOMEM; in pci_save_pcie_state()
1694 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1728 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1733 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1755 return -ENOMEM; in pci_save_pcix_state()
1759 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1774 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1780 * pci_save_state - save the PCI configuration space of a device before
1789 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1791 i * 4, dev->saved_config_space[i]); in pci_save_state()
1793 dev->state_saved = true; in pci_save_state()
1821 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n", in pci_restore_config_dword()
1824 if (retry-- <= 0) in pci_restore_config_dword()
1841 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1843 pdev->saved_config_space[index], in pci_restore_config_space_range()
1849 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1854 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1887 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1896 * pci_restore_state - Restore the saved state of a PCI device
1901 if (!dev->state_saved) in pci_restore_state()
1926 dev->state_saved = false; in pci_restore_state()
1936 * pci_store_saved_state - Allocate and return an opaque struct containing
1949 if (!dev->state_saved) in pci_store_saved_state()
1954 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1955 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1961 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1962 sizeof(state->config_space)); in pci_store_saved_state()
1964 cap = state->cap; in pci_store_saved_state()
1965 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1966 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1967 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1977 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1986 dev->state_saved = false; in pci_load_saved_state()
1991 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1992 sizeof(state->config_space)); in pci_load_saved_state()
1994 cap = state->cap; in pci_load_saved_state()
1995 while (cap->size) { in pci_load_saved_state()
1998 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1999 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
2000 return -EINVAL; in pci_load_saved_state()
2002 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
2004 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
2007 dev->state_saved = true; in pci_load_saved_state()
2013 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
2035 struct pci_host_bridge *host_bridge = pci_find_host_bridge(dev->bus); in pci_host_bridge_enable_device()
2038 if (host_bridge && host_bridge->enable_device) { in pci_host_bridge_enable_device()
2039 err = host_bridge->enable_device(host_bridge, dev); in pci_host_bridge_enable_device()
2049 struct pci_host_bridge *host_bridge = pci_find_host_bridge(dev->bus); in pci_host_bridge_disable_device()
2051 if (host_bridge && host_bridge->disable_device) in pci_host_bridge_disable_device()
2052 host_bridge->disable_device(host_bridge, dev); in pci_host_bridge_disable_device()
2063 if (err < 0 && err != -EIO) in do_pci_enable_device()
2079 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
2100 * pci_reenable_device - Resume abandoned device
2109 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
2124 if (!dev->is_busmaster) in pci_enable_bridge()
2143 * Power state could be unknown at this point, either due to a fresh in pci_enable_device_flags()
2144 * boot or a device removal call. So get the current power state in pci_enable_device_flags()
2148 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
2150 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
2159 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2162 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2167 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2172 * pci_enable_device_mem - Initialize a device for use with Memory space
2175 * Initialize device before it's used by a driver. Ask low-level code
2176 * to enable Memory resources. Wake up the device if it was suspended.
2186 * pci_enable_device - Initialize device before it's used by a driver.
2189 * Initialize device before it's used by a driver. Ask low-level code
2190 * to enable I/O and memory. Wake up the device if it was suspended.
2203 * pcibios_device_add - provide arch specific hooks when adding device dev
2216 * pcibios_release_device - provide arch specific hooks when releasing
2227 * pcibios_disable_device - disable arch specific PCI resources for device dev
2250 * pci_disable_enabled_device - Disable device without updating enable_cnt
2253 * NOTE: This function is a backend of PCI power management routines and is
2263 * pci_disable_device - Disable PCI device after use
2267 * anymore. This only involves disabling PCI bus-mastering, if active.
2274 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2275 "disabling already-disabled device"); in pci_disable_device()
2277 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2284 dev->is_busmaster = 0; in pci_disable_device()
2289 * pcibios_set_pcie_reset_state - set reset state for device dev
2299 return -EINVAL; in pcibios_set_pcie_reset_state()
2303 * pci_set_pcie_reset_state - set reset state for device dev
2326 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2335 * pci_check_pme_status - Check if given device has generated PME.
2348 if (!dev->pm_cap) in pci_check_pme_status()
2351 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2370 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2379 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2380 dev->pme_poll = false; in pci_pme_wakeup()
2384 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2390 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2401 * pci_pme_capable - check the capability of PCI device to generate PME#
2407 if (!dev->pm_cap) in pci_pme_capable()
2410 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2420 struct pci_dev *pdev = pme_dev->dev; in pci_pme_list_scan()
2422 if (pdev->pme_poll) { in pci_pme_list_scan()
2423 struct pci_dev *bridge = pdev->bus->self; in pci_pme_list_scan()
2424 struct device *dev = &pdev->dev; in pci_pme_list_scan()
2425 struct device *bdev = bridge ? &bridge->dev : NULL; in pci_pme_list_scan()
2439 if (bridge->current_state != PCI_D0) in pci_pme_list_scan()
2449 pdev->current_state != PCI_D3cold) in pci_pme_list_scan()
2456 list_del(&pme_dev->list); in pci_pme_list_scan()
2470 if (!dev->pme_support) in __pci_pme_active()
2473 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2479 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2483 * pci_pme_restore - Restore PME configuration after config space restore.
2490 if (!dev->pme_support) in pci_pme_restore()
2493 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2494 if (dev->wakeup_prepared) { in pci_pme_restore()
2501 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2505 * pci_pme_active - enable or disable PCI device's PME# function
2518 * its PME# line hooked up correctly. Not all hardware vendors in pci_pme_active()
2523 * we'll wake up often enough anyway that this won't be a huge in pci_pme_active()
2524 * hit, and the power savings from the devices will still be a in pci_pme_active()
2527 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2536 if (dev->pme_poll) { in pci_pme_active()
2545 pme_dev->dev = dev; in pci_pme_active()
2547 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2556 if (pme_dev->dev == dev) { in pci_pme_active()
2557 list_del(&pme_dev->list); in pci_pme_active()
2571 * __pci_enable_wake - enable PCI device as wakeup event source
2577 * When such events involves platform-specific hooks, those hooks are
2580 * Devices with legacy power management (no standard PCI PM capabilities)
2585 * -EINVAL is returned if device is not supposed to wake up the system
2587 * the native mechanism fail to enable the generation of wake-up events
2594 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2595 * wakeup on behalf of subordinate devices which is set up in __pci_enable_wake()
2597 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2604 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2610 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2621 * the device itself ends up in D3cold as a result of that. in __pci_enable_wake()
2631 dev->wakeup_prepared = true; in __pci_enable_wake()
2635 dev->wakeup_prepared = false; in __pci_enable_wake()
2642 * pci_enable_wake - change wakeup settings for a PCI device
2652 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2653 return -EINVAL; in pci_enable_wake()
2660 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2662 * @enable: True to enable wake-up event generation; false to disable
2664 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2665 * and this function allows them to set that up cleanly - pci_enable_wake()
2666 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2670 * up the system from sleep or it is not capable of generating PME# from both
2671 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2682 * pci_target_state - find an appropriate low power state for a given PCI dev
2686 * Use underlying platform code to find a supported low power state for @dev.
2713 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2714 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2717 if (dev->current_state == PCI_D3cold) in pci_target_state()
2719 else if (!dev->pm_cap) in pci_target_state()
2722 if (wakeup && dev->pme_support) { in pci_target_state()
2729 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2730 state--; in pci_target_state()
2734 else if (dev->pme_support & 1) in pci_target_state()
2742 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2746 * Choose the power state appropriate for the device depending on whether
2747 * it can wake up the system and/or is power manageable by the platform
2752 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2757 return -EIO; in pci_prepare_to_sleep()
2771 * pci_back_from_sleep - turn PCI device on during system-wide transition
2775 * Disable device's system wake-up capability and put it into D0.
2790 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2793 * Prepare @dev to generate wake-up events at run time and put it into a low
2794 * power state.
2801 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2803 return -EIO; in pci_finish_runtime_suspend()
2816 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2819 * Return true if the device itself is capable of generating wake-up events
2821 * PME and one of its upstream bridges can generate wake-up events.
2825 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2827 if (!dev->pme_support) in pci_dev_run_wake()
2830 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2834 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2837 while (bus->parent) { in pci_dev_run_wake()
2838 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2840 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2843 bus = bus->parent; in pci_dev_run_wake()
2847 if (bus->bridge) in pci_dev_run_wake()
2848 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2855 * pci_dev_need_resume - Check if it is necessary to resume the device.
2858 * Return 'true' if the device is not runtime-suspended or it has to be
2860 * suspend, or the current power state of it is not suitable for the upcoming
2861 * (system-wide) transition.
2865 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2874 * If the earlier platform check has not triggered, D3cold is just power in pci_dev_need_resume()
2878 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2880 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2884 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2888 * disable PME for it to prevent it from waking up the system unnecessarily.
2890 * Note that if the device's power state is D3cold and the platform check in
2896 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2898 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2901 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2904 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2908 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2911 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2917 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2922 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2924 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2927 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2931 * pci_choose_state - Choose the power state of a PCI device.
2935 * Returns PCI power state suitable for @dev and @state.
2948 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2949 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2955 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2964 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2970 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2971 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2983 * which allows Linux to power manage it. However, this
2984 * confuses the BIOS SMI handler so don't power manage root
2987 .ident = "X299 DESIGNARE EX-CF",
2990 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3007 * Changing power state of root port dGPU is connected fails
3008 * https://gitlab.freedesktop.org/drm/amd/-/issues/3229
3010 .ident = "Hewlett-Packard HP Pavilion 17 Notebook PC/1972",
3012 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
3022 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3042 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
3044 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
3051 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3063 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3086 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3089 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3101 * pci_bridge_d3_update - Update bridge D3 capabilities
3110 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3122 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3142 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3143 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3146 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3147 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3154 * pci_d3cold_enable - Enable D3cold for device
3163 if (dev->no_d3cold) { in pci_d3cold_enable()
3164 dev->no_d3cold = false; in pci_d3cold_enable()
3171 * pci_d3cold_disable - Disable D3cold for device
3180 if (!dev->no_d3cold) { in pci_d3cold_disable()
3181 dev->no_d3cold = true; in pci_d3cold_disable()
3188 * pci_pm_init - Initialize PM functions of given PCI device
3197 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3198 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3199 pm_runtime_enable(&dev->dev); in pci_pm_init()
3200 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3201 dev->wakeup_prepared = false; in pci_pm_init()
3203 dev->pm_cap = 0; in pci_pm_init()
3204 dev->pme_support = 0; in pci_pm_init()
3219 dev->pm_cap = pm; in pci_pm_init()
3220 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3221 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3222 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3223 dev->d3cold_allowed = true; in pci_pm_init()
3225 dev->d1_support = false; in pci_pm_init()
3226 dev->d2_support = false; in pci_pm_init()
3229 dev->d1_support = true; in pci_pm_init()
3231 dev->d2_support = true; in pci_pm_init()
3233 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3235 dev->d1_support ? " D1" : "", in pci_pm_init()
3236 dev->d2_support ? " D2" : ""); in pci_pm_init()
3247 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc); in pci_pm_init()
3248 dev->pme_poll = true; in pci_pm_init()
3250 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3251 * let the user space enable it to wake up the system as needed. in pci_pm_init()
3253 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3260 dev->imm_ready = 1; in pci_pm_init()
3290 return &dev->resource[bei]; in pci_ea_get_resource()
3294 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3295 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3298 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3358 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3367 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3377 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3399 if (ent_size != ent_offset - offset) { in pci_ea_read()
3401 ent_size, ent_offset - offset); in pci_ea_read()
3405 res->name = pci_name(dev); in pci_ea_read()
3406 res->start = start; in pci_ea_read()
3407 res->end = end; in pci_ea_read()
3408 res->flags = flags; in pci_ea_read()
3441 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3448 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3459 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3463 * _pci_add_cap_save_buffer - allocate buffer for saving given
3486 return -ENOMEM; in _pci_add_cap_save_buffer()
3488 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3489 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3490 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3507 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3521 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3536 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3541 * pci_configure_ari - enable or disable ARI forwarding
3552 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3555 bridge = dev->bus->self; in pci_configure_ari()
3566 bridge->ari_enabled = 1; in pci_configure_ari()
3570 bridge->ari_enabled = 0; in pci_configure_ari()
3579 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3586 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3596 * pci_acs_enabled - test ACS against required flags for a given device
3606 * opportunity for peer-to-peer access. We therefore return 'true'
3620 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3629 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3631 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3645 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3646 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3653 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3662 if (!pdev->multifunction) in pci_acs_enabled()
3676 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3681 * Walk up a device tree from start to end testing PCI ACS support. If
3695 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3698 parent = pdev->bus->self; in pci_acs_path_enabled()
3705 * pci_acs_init - Initialize ACS if hardware supports it
3710 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3722 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3727 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3728 * Returns -ENOENT if no ctrl register for the BAR could be found.
3737 return -ENOTSUPP; in pci_rebar_find_pos()
3751 return -ENOENT; in pci_rebar_find_pos()
3755 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3775 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3784 * pci_rebar_get_current_size - get the current size of a BAR
3805 * pci_rebar_set_size - set a new size for a BAR
3830 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3839 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3844 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3853 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3854 return -EINVAL; in pci_enable_atomic_ops_to_root()
3857 return -EINVAL; in pci_enable_atomic_ops_to_root()
3863 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3872 return -EINVAL; in pci_enable_atomic_ops_to_root()
3875 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3876 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3885 return -EINVAL; in pci_enable_atomic_ops_to_root()
3891 return -EINVAL; in pci_enable_atomic_ops_to_root()
3900 return -EINVAL; in pci_enable_atomic_ops_to_root()
3903 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3913 * pci_release_region - Release a PCI bar
3946 * __pci_request_region - Reserved PCI I/O and memory resource
3993 &pdev->resource[bar]); in __pci_request_region()
3994 return -EBUSY; in __pci_request_region()
3998 * pci_request_region - Reserve PCI I/O and memory resource
4024 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4053 while (--i >= 0) in __pci_request_selected_regions()
4057 return -EBUSY; in __pci_request_selected_regions()
4062 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4082 * pci_request_selected_regions_exclusive - Request regions exclusively
4103 * pci_release_regions - Release reserved PCI I/O and memory resources
4113 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4118 * pci_request_regions - Reserve PCI I/O and memory resources
4137 ((1 << PCI_STD_NUM_BARS) - 1), name); in pci_request_regions()
4142 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4166 ((1 << PCI_STD_NUM_BARS) - 1), name); in pci_request_regions_exclusive()
4182 return -EINVAL; in pci_register_io_range()
4186 return -ENOMEM; in pci_register_io_range()
4188 range->fwnode = fwnode; in pci_register_io_range()
4189 range->size = size; in pci_register_io_range()
4190 range->hw_start = addr; in pci_register_io_range()
4191 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4198 if (ret == -EEXIST) in pci_register_io_range()
4222 return (unsigned long)-1; in pci_address_to_pio()
4229 * pci_remap_iospace - Remap the memory mapped I/O space
4242 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4244 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4245 return -EINVAL; in pci_remap_iospace()
4247 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4248 return -EINVAL; in pci_remap_iospace()
4258 return -ENODEV; in pci_remap_iospace()
4265 * pci_unmap_iospace - Unmap the memory mapped I/O space
4275 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4296 dev->is_busmaster = enable; in __pci_set_master()
4300 * pcibios_setup - process "pci=" kernel boot arguments
4312 * pcibios_set_master - enable PCI bus-mastering for device dev
4315 * Enables PCI bus-mastering for the device. This is the default
4339 * pci_set_master - enables bus-mastering for device dev
4342 * Enables bus-mastering on the device and calls pcibios_set_master()
4353 * pci_clear_master - disables bus-mastering for device dev
4363 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4368 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4370 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4377 return -EINVAL; in pci_set_cacheline_size()
4396 return -EINVAL; in pci_set_cacheline_size()
4401 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4404 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4406 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4422 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4432 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4435 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4438 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4451 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4454 * Disables PCI Memory-Write-Invalidate transaction on the device
4471 * pci_disable_parity - disable parity checking for device
4488 * pci_intx - enables/disables PCI INTx for device dev
4513 * pci_wait_for_pending_transaction - wait for pending transaction
4529 * pcie_flr - initiate a PCIe function level reset
4542 if (dev->imm_ready) in pcie_flr()
4547 * 100ms, but may silently discard requests while the FLR is in in pcie_flr()
4548 * progress. Wait 100ms before trying to access the device. in pcie_flr()
4557 * pcie_reset_flr - initiate a PCIe function level reset
4565 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4566 return -ENOTTY; in pcie_reset_flr()
4568 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4569 return -ENOTTY; in pcie_reset_flr()
4585 return -ENOTTY; in pci_af_flr()
4587 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4588 return -ENOTTY; in pci_af_flr()
4592 return -ENOTTY; in pci_af_flr()
4598 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4608 if (dev->imm_ready) in pci_af_flr()
4614 * 100ms, but may silently discard requests while the FLR is in in pci_af_flr()
4615 * progress. Wait 100ms before trying to access the device. in pci_af_flr()
4623 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4629 * PCI_D0. If that's the case and the device is not in a low-power state
4632 * NOTE: This causes the caller to sleep for twice the device power transition
4633 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4641 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4642 return -ENOTTY; in pci_pm_reset()
4644 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4646 return -ENOTTY; in pci_pm_reset()
4651 if (dev->current_state != PCI_D0) in pci_pm_reset()
4652 return -EINVAL; in pci_pm_reset()
4656 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4661 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4664 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4668 * pcie_wait_for_link_status - Wait for link status change
4673 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
4694 return -ETIMEDOUT; in pcie_wait_for_link_status()
4698 * pcie_retrain_link - Request a link retrain and wait for it to complete
4706 * Return 0 if successful, or -ETIMEDOUT if training has not completed
4725 if (pdev->clear_retrain_link) { in pcie_retrain_link()
4746 * pcie_wait_for_link_delay - Wait until link is active or inactive
4749 * @delay: Delay to wait after link has become active (in ms)
4754 int delay) in pcie_wait_for_link_delay() argument
4760 * case, we wait for 1000 ms + any delay requested by the caller. in pcie_wait_for_link_delay()
4762 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
4763 msleep(PCIE_LINK_RETRAIN_TIMEOUT_MS + delay); in pcie_wait_for_link_delay()
4768 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, in pcie_wait_for_link_delay()
4770 * successful. If so, software must wait a minimum 100ms before sending in pcie_wait_for_link_delay()
4785 msleep(delay); in pcie_wait_for_link_delay()
4796 * pcie_wait_for_link - Wait until link is active or inactive
4808 * Find maximum D3cold delay required by all the devices on the bus. The
4809 * spec says 100 ms, but firmware can lower it and we allow drivers to
4820 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
4821 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
4822 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4823 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
4824 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4831 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4833 * @reset_type: reset type in human-readable form
4843 * Return 0 on success or -ENOTTY if the first device on the secondary bus
4849 int delay; in pci_bridge_wait_for_secondary_bus() local
4861 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
4865 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
4871 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
4872 if (!delay) { in pci_bridge_wait_for_secondary_bus()
4877 child = pci_dev_get(list_first_entry(&dev->subordinate->devices, in pci_bridge_wait_for_secondary_bus()
4882 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
4883 * accessing the device after reset (that is 1000 ms + 100 ms). in pci_bridge_wait_for_secondary_bus()
4886 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); in pci_bridge_wait_for_secondary_bus()
4887 msleep(1000 + delay); in pci_bridge_wait_for_secondary_bus()
4893 * greater than 5 GT/s need to wait minimum 100 ms. For higher in pci_bridge_wait_for_secondary_bus()
4897 * However, 100 ms is the minimum and the PCIe spec says the in pci_bridge_wait_for_secondary_bus()
4903 * Therefore we wait for 100 ms and check for the device presence in pci_bridge_wait_for_secondary_bus()
4912 pci_dbg(dev, "waiting %d ms for downstream link\n", delay); in pci_bridge_wait_for_secondary_bus()
4913 msleep(delay); in pci_bridge_wait_for_secondary_bus()
4915 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay)) in pci_bridge_wait_for_secondary_bus()
4923 if (!dev->link_active_reporting) in pci_bridge_wait_for_secondary_bus()
4924 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4928 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4931 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT); in pci_bridge_wait_for_secondary_bus()
4934 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", in pci_bridge_wait_for_secondary_bus()
4935 delay); in pci_bridge_wait_for_secondary_bus()
4936 if (!pcie_wait_for_link_delay(dev, true, delay)) { in pci_bridge_wait_for_secondary_bus()
4939 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4943 PCIE_RESET_READY_POLL_MS - delay); in pci_bridge_wait_for_secondary_bus()
4955 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double in pci_reset_secondary_bus()
4956 * this to 2ms to ensure that we meet the minimum requirement. in pci_reset_secondary_bus()
4970 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4974 * Devices on the secondary bus are left in power-on state.
4978 if (!dev->block_cfg_access) in pci_bridge_secondary_bus_reset()
4991 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
4992 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
4993 return -ENOTTY; in pci_parent_bus_reset()
4995 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
4997 return -ENOTTY; in pci_parent_bus_reset()
5002 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5007 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5009 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5012 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5013 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5015 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5022 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5023 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5024 return -ENOTTY; in pci_dev_reset_slot_function()
5026 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5072 return -ENOTTY; in pci_reset_bus_function()
5076 if (rc != -ENOTTY) in pci_reset_bus_function()
5089 return -ENOTTY; in cxl_reset_bus_function()
5093 return -ENOTTY; in cxl_reset_bus_function()
5100 return -ENOTTY; in cxl_reset_bus_function()
5122 device_lock(&dev->dev); in pci_dev_lock()
5130 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5133 device_unlock(&dev->dev); in pci_dev_trylock()
5143 device_unlock(&dev->dev); in pci_dev_unlock()
5150 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5153 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5154 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5157 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5158 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5159 else if (dev->driver) in pci_dev_save_and_disable()
5163 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5165 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5172 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5174 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5175 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5183 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5188 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5189 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5192 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5193 err_handler->reset_done(dev); in pci_dev_restore()
5194 else if (dev->driver) in pci_dev_restore()
5198 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5211 * __pci_reset_function_locked - reset a PCI device function while holding
5237 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5245 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5247 return -ENOTTY; in __pci_reset_function_locked()
5252 if (rc != -ENOTTY) in __pci_reset_function_locked()
5256 return -ENOTTY; in __pci_reset_function_locked()
5261 * pci_init_reset_methods - check whether device can be safely reset
5266 * other functions in the same device. The PCI device must be in D0-D3hot
5284 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5285 else if (rc != -ENOTTY) in pci_init_reset_methods()
5289 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5293 * pci_reset_function - quiesce and reset a PCI device function
5314 return -ENOTTY; in pci_reset_function()
5340 * pci_reset_function_locked - quiesce and reset a PCI device function
5361 return -ENOTTY; in pci_reset_function_locked()
5374 * pci_try_reset_function - quiesce and reset a PCI device function
5377 * Same as above, except return -EAGAIN if unable to lock device.
5384 return -ENOTTY; in pci_try_reset_function()
5387 return -EAGAIN; in pci_try_reset_function()
5404 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resettable()
5407 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resettable()
5408 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resettable()
5409 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_bus_resettable()
5421 pci_dev_lock(bus->self); in pci_bus_lock()
5422 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5423 if (dev->subordinate) in pci_bus_lock()
5424 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5430 /* Unlock devices from the bottom of the tree up */
5435 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5436 if (dev->subordinate) in pci_bus_unlock()
5437 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5441 pci_dev_unlock(bus->self); in pci_bus_unlock()
5449 if (!pci_dev_trylock(bus->self)) in pci_bus_trylock()
5452 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5453 if (dev->subordinate) { in pci_bus_trylock()
5454 if (!pci_bus_trylock(dev->subordinate)) in pci_bus_trylock()
5462 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5463 if (dev->subordinate) in pci_bus_trylock()
5464 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5468 pci_dev_unlock(bus->self); in pci_bus_trylock()
5477 if (slot->bus->self && in pci_slot_resettable()
5478 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resettable()
5481 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resettable()
5482 if (!dev->slot || dev->slot != slot) in pci_slot_resettable()
5484 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resettable()
5485 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_slot_resettable()
5497 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5498 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5500 if (dev->subordinate) in pci_slot_lock()
5501 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5507 /* Unlock devices from the bottom of the tree up */
5512 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5513 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5515 if (dev->subordinate) in pci_slot_unlock()
5516 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5526 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5527 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5529 if (dev->subordinate) { in pci_slot_trylock()
5530 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5541 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5542 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5544 if (dev->subordinate) in pci_slot_trylock()
5545 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5560 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5562 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5563 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5576 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5578 if (dev->subordinate) { in pci_bus_restore_locked()
5580 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5593 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5594 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5597 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5598 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5611 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5612 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5615 if (dev->subordinate) { in pci_slot_restore_locked()
5617 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5627 return -ENOTTY; in pci_slot_reset()
5634 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5643 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5655 * __pci_reset_slot - Try to reset a PCI slot
5659 * independent of other slots. For instance, some slots may support slot power
5667 * Same as above except return -EAGAIN if the slot cannot be locked
5680 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5684 rc = -EAGAIN; in __pci_reset_slot()
5693 if (!bus->self || !pci_bus_resettable(bus)) in pci_bus_reset()
5694 return -ENOTTY; in pci_bus_reset()
5703 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5711 * pci_bus_error_reset - reset the bridge's subordinate bus
5720 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5724 return -ENOTTY; in pci_bus_error_reset()
5727 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5730 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5734 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5742 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
5746 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5758 * __pci_reset_bus - Try to reset a PCI bus
5761 * Same as above except return -EAGAIN if the bus cannot be locked
5774 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
5778 rc = -EAGAIN; in __pci_reset_bus()
5784 * pci_reset_bus - Try to reset a PCI bus
5787 * Same as above except return -EAGAIN if the bus cannot be locked
5791 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
5792 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
5797 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5810 return -EINVAL; in pcix_get_max_mmrbc()
5813 return -EINVAL; in pcix_get_max_mmrbc()
5820 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5833 return -EINVAL; in pcix_get_mmrbc()
5836 return -EINVAL; in pcix_get_mmrbc()
5843 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5858 return -EINVAL; in pcix_set_mmrbc()
5860 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
5864 return -EINVAL; in pcix_set_mmrbc()
5867 return -EINVAL; in pcix_set_mmrbc()
5870 return -E2BIG; in pcix_set_mmrbc()
5873 return -EINVAL; in pcix_set_mmrbc()
5877 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
5878 return -EIO; in pcix_set_mmrbc()
5883 return -EIO; in pcix_set_mmrbc()
5890 * pcie_get_readrq - get PCI Express read request size
5906 * pcie_set_readrq - set PCI Express maximum memory read request
5917 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); in pcie_set_readrq()
5920 return -EINVAL; in pcie_set_readrq()
5934 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8); in pcie_set_readrq()
5936 if (bridge->no_inc_mrrs) { in pcie_set_readrq()
5941 return -EINVAL; in pcie_set_readrq()
5953 * pcie_get_mps - get PCI Express maximum payload size
5969 * pcie_set_mps - set PCI Express maximum payload size
5982 return -EINVAL; in pcie_set_mps()
5984 v = ffs(mps) - 8; in pcie_set_mps()
5985 if (v > dev->pcie_mpss) in pcie_set_mps()
5986 return -EINVAL; in pcie_set_mps()
6015 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6022 * Walk up the PCI device chain and find the point where the minimum
6072 * pcie_get_supported_speeds - query Supported Link Speed Vector
6108 /* PCIe r3.0-compliant */ in pcie_get_supported_speeds()
6122 * pcie_get_speed_cap - query for the PCI device's link speed capability
6131 return PCIE_LNKCAP2_SLS2SPEED(dev->supported_speeds); in pcie_get_speed_cap()
6136 * pcie_get_width_cap - query for the PCI device's link width capability
6155 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6178 * __pcie_print_link_status - Report the PCI device's link speed and width
6211 * pcie_print_link_status - Report the PCI device's link speed and width
6223 * pci_select_bars - Make BAR mask from the type of resource
6257 * pci_set_vga_state - set VGA decode state on device and parents if requested
6291 bus = dev->bus; in pci_set_vga_state()
6293 bridge = bus->self; in pci_set_vga_state()
6304 bus = bus->parent; in pci_set_vga_state()
6317 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6321 return adev->power.flags.power_resources && in pci_pr3_present()
6322 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6328 * pci_add_dma_alias - Add a DMA devfn alias for a device
6333 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6334 * which is used to program permissible bus-devfn source addresses for DMA
6337 * from their logical bus-devfn. Examples include device quirks where the
6338 * device simply uses the wrong devfn, as well as non-transparent bridges
6352 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6353 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6355 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6356 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6357 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6362 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6375 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6376 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6377 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6378 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6391 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6397 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6399 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6402 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6407 * pci_real_dma_dev - Get PCI DMA device for PCI device
6410 * Permits the platform to provide architecture-specific functionality to
6427 * Arches that don't want to expose struct resource to userland as-is in
6434 *start = rsrc->start; in pci_resource_to_user()
6435 *end = rsrc->end; in pci_resource_to_user()
6442 * pci_specified_resource_alignment - get resource alignment specified by user.
6506 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6510 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6513 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6540 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6555 r->start = 0; in pci_request_resource_alignment()
6556 r->end = align - 1; in pci_request_resource_alignment()
6558 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6559 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6562 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6568 * It also rounds up size to specified alignment.
6569 * Later on, the kernel will assign page-aligned memory resource back
6581 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6583 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6586 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6594 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6595 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6612 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6614 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6615 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6617 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6618 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6619 r->start = 0; in pci_reassigndev_resource_alignment()
6642 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6643 return -EINVAL; in resource_alignment_store()
6647 return -ENOMEM; in resource_alignment_store()
6723 domain_nr = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6745 if (of_get_pci_domain_nr(parent->of_node) == domain_nr) in of_pci_bus_release_domain_nr()
6766 * pci_ext_cfg_avail - can we access extended PCI config space?