Lines Matching refs:p_slot
69 struct slot *p_slot;
148 int shpchp_configure_device(struct slot *p_slot);
149 void shpchp_unconfigure_device(struct slot *p_slot);
210 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
215 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
217 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
225 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
228 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
237 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
240 ctrl_dbg(p_slot->ctrl,
244 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
248 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
251 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
253 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
256 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
258 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
263 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
268 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
273 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
278 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
282 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);