28 static int to_debug = 0;
29 #define debug_polling(fmt, arg...)	do { if (to_debug) debug(fmt, arg); } while (0)
43 #define WPG_I2CMBUFL_OFFSET	0x08	// I2C Message Buffer Low
44 #define WPG_I2CMOSUP_OFFSET	0x10	// I2C Master Operation Setup Reg
45 #define WPG_I2CMCNTL_OFFSET	0x20	// I2C Master Control Register
46 #define WPG_I2CPARM_OFFSET	0x40	// I2C Parameter Register
47 #define WPG_I2CSTAT_OFFSET	0x70	// I2C Status Register
52 #define WPG_I2C_AND		0x1000	// I2C AND operation
53 #define WPG_I2C_OR		0x2000	// I2C OR operation
58 #define WPG_READATADDR_MASK	0x00010000	// read,bytes,I2C shifted,index
59 #define WPG_WRITEATADDR_MASK	0x40010000	// write,bytes,I2C shifted,index
60 #define WPG_READDIRECT_MASK	0x10010000
61 #define WPG_WRITEDIRECT_MASK	0x60010000
67 #define WPG_I2CMCNTL_STARTOP_MASK	0x00000002	// Start the Operation
72 #define WPG_I2C_IOREMAP_SIZE	0x2044	// size of linear address interval
77 #define WPG_1ST_SLOT_INDEX	0x01	// index - 1st slot for ctlr
78 #define WPG_CTLR_INDEX		0x0F	// index - ctlr
79 #define WPG_1ST_EXTSLOT_INDEX	0x10	// index - 1st ext slot for ctlr
80 #define WPG_1ST_BUS_INDEX	0x1F	// index - 1st bus for ctlr
86 #define HPC_I2CSTATUS_CHECK(s)	((u8)((s & 0x00000A76) ? 0 : 1))
133 	if (ctlr_ptr->ctlr_type == 0x02) {  in i2c_ctrl_read()
142 	} else if (ctlr_ptr->ctlr_type == 0x04) {  in i2c_ctrl_read()
160 	data = 0x00000000;  in i2c_ctrl_read()
167 	//                 2020 : [20] OR operation at [20] offset 0x20  in i2c_ctrl_read()
185 	if (i == 0) {  in i2c_ctrl_read()
201 	if (i == 0) {  in i2c_ctrl_read()
224 * Return   0 or error codes
237 	rc = 0;  in i2c_ctrl_write()
242 	data = 0x00000000;  in i2c_ctrl_write()
244 	if (ctlr_ptr->ctlr_type == 0x02) {  in i2c_ctrl_write()
253 	} else if (ctlr_ptr->ctlr_type == 0x04) {  in i2c_ctrl_write()
271 	data = 0x00000000 | (unsigned long)cmd;  in i2c_ctrl_write()
278 	//                 2020 : [20] OR operation at [20] offset 0x20  in i2c_ctrl_write()
296 	if (i == 0) {  in i2c_ctrl_write()
313 	if (i == 0) {  in i2c_ctrl_write()
350 	u8 data = 0x00;  in pci_ctrl_read()
363 		rc = 0;  in pci_ctrl_write()
372 	case 0:  in ctrl_read()
390 	u8 rc = 0;  in ctrl_write()
392 	case 0:  in ctrl_write()
419 	case HPC_CTLR_ENABLEIRQ:	// 0x00.N.15  in hpc_writecmdtoindex()
420 	case HPC_CTLR_CLEARIRQ:	// 0x06.N.15  in hpc_writecmdtoindex()
421 	case HPC_CTLR_RESET:	// 0x07.N.15  in hpc_writecmdtoindex()
422 	case HPC_CTLR_IRQSTEER:	// 0x08.N.15  in hpc_writecmdtoindex()
423 	case HPC_CTLR_DISABLEIRQ:	// 0x01.N.15  in hpc_writecmdtoindex()
424 	case HPC_ALLSLOT_ON:	// 0x11.N.15  in hpc_writecmdtoindex()
425 	case HPC_ALLSLOT_OFF:	// 0x12.N.15  in hpc_writecmdtoindex()
426 		rc = 0x0F;  in hpc_writecmdtoindex()
429 	case HPC_SLOT_OFF:	// 0x02.Y.0-14  in hpc_writecmdtoindex()
430 	case HPC_SLOT_ON:	// 0x03.Y.0-14  in hpc_writecmdtoindex()
431 	case HPC_SLOT_ATTNOFF:	// 0x04.N.0-14  in hpc_writecmdtoindex()
432 	case HPC_SLOT_ATTNON:	// 0x05.N.0-14  in hpc_writecmdtoindex()
433 	case HPC_SLOT_BLINKLED:	// 0x13.N.0-14  in hpc_writecmdtoindex()
466 		rc = 0x0F;  in hpc_readcmdtoindex()
479 		rc = 0x28;  in hpc_readcmdtoindex()
482 		rc = 0x25;  in hpc_readcmdtoindex()
485 		rc = 0x27;  in hpc_readcmdtoindex()
501 * Return   0 or error codes
508 	int rc = 0;  in ibmphp_hpc_readslot()
522 		if (busindex < 0) {  in ibmphp_hpc_readslot()
648 	int rc = 0;  in ibmphp_hpc_writeslot()
662 		if (busindex < 0) {  in ibmphp_hpc_writeslot()
705 		done = 0;  in ibmphp_hpc_writeslot()
775 	to_debug = 0;  in ibmphp_unlock_operations()
782 #define POLL_LATCH_REGISTER	0
791 	u8 oldlatchlow = 0x00;  in poll_hpc()
792 	u8 curlatchlow = 0x00;  in poll_hpc()
793 	int poll_count = 0;  in poll_hpc()
794 	u8 ctrl_count = 0x00;  in poll_hpc()
805 			ctrl_count = 0x00;  in poll_hpc()
837 			ctrl_count = 0x00;  in poll_hpc()
864 				poll_count = 0;  in poll_hpc()
878 	return 0;  in poll_hpc()
889 * Return   0 or error codes
900 	int rc = 0;  in process_changeinstatus()
901 	u8 disable = 0;  in process_changeinstatus()
902 	u8 update = 0;  in process_changeinstatus()
906 	// bit 0 - HPC_SLOT_POWER  in process_changeinstatus()
907 	if ((pslot->status & 0x01) != (poldslot->status & 0x01))  in process_changeinstatus()
914 	if ((pslot->status & 0x04) != (poldslot->status & 0x04))  in process_changeinstatus()
919 	if (((pslot->status & 0x08) != (poldslot->status & 0x08))  in process_changeinstatus()
920 		|| ((pslot->status & 0x10) != (poldslot->status & 0x10)))  in process_changeinstatus()
924 	if ((pslot->status & 0x20) != (poldslot->status & 0x20))  in process_changeinstatus()
926 …if ((poldslot->status & 0x20) && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_P…  in process_changeinstatus()
933 	if ((pslot->status & 0x80) != (poldslot->status & 0x80)) {  in process_changeinstatus()
936 		if (pslot->status & 0x80) {  in process_changeinstatus()
956 	if ((pslot->ext_status & 0x08) != (poldslot->ext_status & 0x08))  in process_changeinstatus()
961 		pslot->flag = 0;  in process_changeinstatus()
980 * Return   0 or error codes
988 	int rc = 0;  in process_changeinlatch()
991 	// bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots  in process_changeinlatch()
994 		mask = 0x01 << i;  in process_changeinlatch()
1026 	return 0;  in ibmphp_hpc_start_poll_thread()
1063 * Return   0, HPC_ERROR
1069 	int rc = 0;  in hpc_wait_ctlr_notworking()
1070 	u8 done = 0;  in hpc_wait_ctlr_notworking()