Lines Matching +full:pcie +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <linux/pci-ecam.h>
35 /* Egress - Bridge translation registers */
45 /* Ingress - address translations */
53 /* Rxed msg fifo - Interrupt status registers */
64 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
73 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
106 #define MSGF_LEG_SR_INTB BIT(1)
124 #define BREG_ENABLE_FORCE BIT(1)
141 #define PHY_RDY_LINKUP_BIT BIT(1)
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
200 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
207 if (nwl_phy_link_up(pcie)) in nwl_wait_for_link()
213 return -ETIMEDOUT; in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device() local
222 if (!nwl_pcie_link_up(pcie)) in nwl_pcie_valid_device()
232 * nwl_pcie_map_bus - Get configuration base
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus() local
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
252 /* PCIe operations */
261 struct nwl_pcie *pcie = data; in nwl_pcie_misc_handler() local
262 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_misc_handler()
290 dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
299 dev_err_ratelimited(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); in nwl_pcie_misc_handler()
319 struct nwl_pcie *pcie; in nwl_pcie_leg_handler() local
324 pcie = irq_desc_get_handler_data(desc); in nwl_pcie_leg_handler()
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_leg_handler()
329 generic_handle_domain_irq(pcie->intx_irq_domain, bit); in nwl_pcie_leg_handler()
335 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) in nwl_pcie_handle_msi_irq() argument
337 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { in nwl_pcie_handle_msi_irq()
343 nwl_bridge_writel(pcie, 1 << bit, status_reg); in nwl_pcie_handle_msi_irq()
344 generic_handle_domain_irq(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_high() local
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); in nwl_pcie_msi_handler_high()
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_low() local
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); in nwl_pcie_msi_handler_low()
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_mask_intx_irq() local
376 mask = 1 << data->hwirq; in nwl_mask_intx_irq()
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_mask_intx_irq()
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); in nwl_mask_intx_irq()
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_intx_irq()
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_unmask_intx_irq() local
390 mask = 1 << data->hwirq; in nwl_unmask_intx_irq()
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_unmask_intx_irq()
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); in nwl_unmask_intx_irq()
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_intx_irq()
409 irq_set_chip_data(irq, domain->host_data); in nwl_intx_map()
433 .prefix = "nwl-",
441 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_compose_msi_msg() local
442 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
444 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
445 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
446 msg->data = data->hwirq; in nwl_compose_msi_msg()
457 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc() local
458 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
462 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
463 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
466 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
467 return -ENOSPC; in nwl_irq_domain_alloc()
472 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
475 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
483 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_irq_domain_free() local
484 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
486 mutex_lock(&msi->lock); in nwl_irq_domain_free()
487 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
489 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
497 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_msi_irq_domain() argument
500 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
501 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
505 .host_data = pcie, in nwl_pcie_init_msi_irq_domain()
509 msi->dev_domain = msi_create_parent_irq_domain(&info, &nwl_msi_parent_ops); in nwl_pcie_init_msi_irq_domain()
510 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
512 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
518 static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i) in nwl_pcie_phy_power_off() argument
520 int err = phy_power_off(pcie->phy[i]); in nwl_pcie_phy_power_off()
523 dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i, in nwl_pcie_phy_power_off()
527 static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i) in nwl_pcie_phy_exit() argument
529 int err = phy_exit(pcie->phy[i]); in nwl_pcie_phy_exit()
532 dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err); in nwl_pcie_phy_exit()
535 static int nwl_pcie_phy_enable(struct nwl_pcie *pcie) in nwl_pcie_phy_enable() argument
539 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_phy_enable()
540 ret = phy_init(pcie->phy[i]); in nwl_pcie_phy_enable()
544 ret = phy_power_on(pcie->phy[i]); in nwl_pcie_phy_enable()
546 nwl_pcie_phy_exit(pcie, i); in nwl_pcie_phy_enable()
554 while (i--) { in nwl_pcie_phy_enable()
555 nwl_pcie_phy_power_off(pcie, i); in nwl_pcie_phy_enable()
556 nwl_pcie_phy_exit(pcie, i); in nwl_pcie_phy_enable()
562 static void nwl_pcie_phy_disable(struct nwl_pcie *pcie) in nwl_pcie_phy_disable() argument
566 for (i = ARRAY_SIZE(pcie->phy); i--;) { in nwl_pcie_phy_disable()
567 nwl_pcie_phy_power_off(pcie, i); in nwl_pcie_phy_disable()
568 nwl_pcie_phy_exit(pcie, i); in nwl_pcie_phy_disable()
572 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_irq_domain() argument
574 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
575 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
581 return -EINVAL; in nwl_pcie_init_irq_domain()
584 pcie->intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX, in nwl_pcie_init_irq_domain()
585 &intx_domain_ops, pcie); in nwl_pcie_init_irq_domain()
587 if (!pcie->intx_irq_domain) { in nwl_pcie_init_irq_domain()
589 return -ENOMEM; in nwl_pcie_init_irq_domain()
592 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
593 nwl_pcie_init_msi_irq_domain(pcie); in nwl_pcie_init_irq_domain()
597 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) in nwl_pcie_enable_msi() argument
599 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
601 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
605 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
608 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
609 if (msi->irq_msi1 < 0) in nwl_pcie_enable_msi()
610 return -EINVAL; in nwl_pcie_enable_msi()
612 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
613 nwl_pcie_msi_handler_high, pcie); in nwl_pcie_enable_msi()
616 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
617 if (msi->irq_msi0 < 0) in nwl_pcie_enable_msi()
618 return -EINVAL; in nwl_pcie_enable_msi()
620 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
621 nwl_pcie_msi_handler_low, pcie); in nwl_pcie_enable_msi()
624 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; in nwl_pcie_enable_msi()
627 return -EIO; in nwl_pcie_enable_msi()
631 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
635 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
639 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
640 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
641 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
647 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
649 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & in nwl_pcie_enable_msi()
652 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
658 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & in nwl_pcie_enable_msi()
663 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
668 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) in nwl_pcie_bridge_init() argument
670 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
675 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; in nwl_pcie_bridge_init()
682 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
684 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
688 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, in nwl_pcie_bridge_init()
692 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
696 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); in nwl_pcie_bridge_init()
699 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, in nwl_pcie_bridge_init()
702 /* This routes the PCIe DMA traffic to go through CCI path */ in nwl_pcie_bridge_init()
703 if (of_dma_is_coherent(dev->of_node)) in nwl_pcie_bridge_init()
704 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | in nwl_pcie_bridge_init()
707 err = nwl_wait_for_link(pcie); in nwl_pcie_bridge_init()
711 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; in nwl_pcie_bridge_init()
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
721 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); in nwl_pcie_bridge_init()
724 nwl_bridge_writel(pcie, ecam_val, E_ECAM_CONTROL); in nwl_pcie_bridge_init()
726 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
728 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
731 if (nwl_pcie_link_up(pcie)) in nwl_pcie_bridge_init()
737 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
738 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
739 return -EINVAL; in nwl_pcie_bridge_init()
741 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
743 "nwl_pcie:misc", pcie); in nwl_pcie_bridge_init()
746 pcie->irq_misc); in nwl_pcie_bridge_init()
751 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
754 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
758 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
761 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
764 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
768 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
771 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | in nwl_pcie_bridge_init()
777 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, in nwl_pcie_parse_dt() argument
780 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
785 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
786 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
787 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
788 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
791 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
792 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
793 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
794 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
797 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
798 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
799 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
800 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
803 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
804 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
805 return pcie->irq_intx; in nwl_pcie_parse_dt()
807 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
808 nwl_pcie_leg_handler, pcie); in nwl_pcie_parse_dt()
811 for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) { in nwl_pcie_parse_dt()
812 pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); in nwl_pcie_parse_dt()
813 if (PTR_ERR(pcie->phy[i]) == -ENODEV) { in nwl_pcie_parse_dt()
814 pcie->phy[i] = NULL; in nwl_pcie_parse_dt()
818 if (IS_ERR(pcie->phy[i])) in nwl_pcie_parse_dt()
819 return PTR_ERR(pcie->phy[i]); in nwl_pcie_parse_dt()
826 { .compatible = "xlnx,nwl-pcie-2.11", },
832 struct device *dev = &pdev->dev; in nwl_pcie_probe()
833 struct nwl_pcie *pcie; in nwl_pcie_probe() local
837 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in nwl_pcie_probe()
839 return -ENODEV; in nwl_pcie_probe()
841 pcie = pci_host_bridge_priv(bridge); in nwl_pcie_probe()
842 platform_set_drvdata(pdev, pcie); in nwl_pcie_probe()
844 pcie->dev = dev; in nwl_pcie_probe()
846 err = nwl_pcie_parse_dt(pcie, pdev); in nwl_pcie_probe()
852 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
853 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
854 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
856 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
858 dev_err(dev, "can't enable PCIe ref clock\n"); in nwl_pcie_probe()
862 err = nwl_pcie_phy_enable(pcie); in nwl_pcie_probe()
868 err = nwl_pcie_bridge_init(pcie); in nwl_pcie_probe()
874 err = nwl_pcie_init_irq_domain(pcie); in nwl_pcie_probe()
880 bridge->sysdata = pcie; in nwl_pcie_probe()
881 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
884 err = nwl_pcie_enable_msi(pcie); in nwl_pcie_probe()
896 nwl_pcie_phy_disable(pcie); in nwl_pcie_probe()
898 clk_disable_unprepare(pcie->clk); in nwl_pcie_probe()
904 struct nwl_pcie *pcie = platform_get_drvdata(pdev); in nwl_pcie_remove() local
906 nwl_pcie_phy_disable(pcie); in nwl_pcie_remove()
907 clk_disable_unprepare(pcie->clk); in nwl_pcie_remove()
912 .name = "nwl-pcie",