Lines Matching +full:versal +full:- +full:cpm5 +full:- +full:host
1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
5 * (C) Copyright 2019 - 2020, Xilinx, Inc.
21 #include "pcie-xilinx-common.h"
85 CPM5, enumerator
91 * struct xilinx_cpm_variant - CPM variant information
94 * @ir_enable: Offset for the CPM5 local error interrupt enable register
105 * struct xilinx_cpm_pcie - PCIe port information
132 return readl_relaxed(port->reg_base + reg); in pcie_read()
138 writel_relaxed(val, port->reg_base + reg); in pcie_write()
152 dev_dbg(port->dev, "Requester ID %lu\n", in cpm_pcie_clear_err_interrupts()
166 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT); in xilinx_cpm_mask_leg_irq()
167 raw_spin_lock_irqsave(&port->lock, flags); in xilinx_cpm_mask_leg_irq()
170 raw_spin_unlock_irqrestore(&port->lock, flags); in xilinx_cpm_mask_leg_irq()
180 mask = BIT(data->hwirq + XILINX_CPM_PCIE_IDRN_SHIFT); in xilinx_cpm_unmask_leg_irq()
181 raw_spin_lock_irqsave(&port->lock, flags); in xilinx_cpm_unmask_leg_irq()
184 raw_spin_unlock_irqrestore(&port->lock, flags); in xilinx_cpm_unmask_leg_irq()
194 * xilinx_cpm_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
206 irq_set_chip_data(irq, domain->host_data); in xilinx_cpm_pcie_intx_map()
230 generic_handle_domain_irq(port->intx_domain, i); in xilinx_cpm_pcie_intx_flow()
240 raw_spin_lock(&port->lock); in xilinx_cpm_mask_event_irq()
242 val &= ~BIT(d->hwirq); in xilinx_cpm_mask_event_irq()
244 raw_spin_unlock(&port->lock); in xilinx_cpm_mask_event_irq()
252 raw_spin_lock(&port->lock); in xilinx_cpm_unmask_event_irq()
254 val |= BIT(d->hwirq); in xilinx_cpm_unmask_event_irq()
256 raw_spin_unlock(&port->lock); in xilinx_cpm_unmask_event_irq()
260 .name = "RC-Event",
270 irq_set_chip_data(irq, domain->host_data); in xilinx_cpm_pcie_event_map()
283 const struct xilinx_cpm_variant *variant = port->variant; in xilinx_cpm_pcie_event_flow()
291 generic_handle_domain_irq(port->cpm_domain, i); in xilinx_cpm_pcie_event_flow()
294 if (variant->ir_status) { in xilinx_cpm_pcie_event_flow()
295 val = readl_relaxed(port->cpm_base + variant->ir_status); in xilinx_cpm_pcie_event_flow()
297 writel_relaxed(val, port->cpm_base + in xilinx_cpm_pcie_event_flow()
298 variant->ir_status); in xilinx_cpm_pcie_event_flow()
305 val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS); in xilinx_cpm_pcie_event_flow()
308 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_STATUS); in xilinx_cpm_pcie_event_flow()
344 struct device *dev = port->dev; in xilinx_cpm_pcie_intr_handler()
347 d = irq_domain_get_irq_data(port->cpm_domain, irq); in xilinx_cpm_pcie_intr_handler()
349 switch (d->hwirq) { in xilinx_cpm_pcie_intr_handler()
357 if (intr_cause[d->hwirq].str) in xilinx_cpm_pcie_intr_handler()
358 dev_warn(dev, "%s\n", intr_cause[d->hwirq].str); in xilinx_cpm_pcie_intr_handler()
360 dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq); in xilinx_cpm_pcie_intr_handler()
368 if (port->intx_domain) { in xilinx_cpm_free_irq_domains()
369 irq_domain_remove(port->intx_domain); in xilinx_cpm_free_irq_domains()
370 port->intx_domain = NULL; in xilinx_cpm_free_irq_domains()
373 if (port->cpm_domain) { in xilinx_cpm_free_irq_domains()
374 irq_domain_remove(port->cpm_domain); in xilinx_cpm_free_irq_domains()
375 port->cpm_domain = NULL; in xilinx_cpm_free_irq_domains()
380 * xilinx_cpm_pcie_init_irq_domain - Initialize IRQ domain
387 struct device *dev = port->dev; in xilinx_cpm_pcie_init_irq_domain()
388 struct device_node *node = dev->of_node; in xilinx_cpm_pcie_init_irq_domain()
395 return -EINVAL; in xilinx_cpm_pcie_init_irq_domain()
398 port->cpm_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), 32, in xilinx_cpm_pcie_init_irq_domain()
400 if (!port->cpm_domain) in xilinx_cpm_pcie_init_irq_domain()
403 irq_domain_update_bus_token(port->cpm_domain, DOMAIN_BUS_NEXUS); in xilinx_cpm_pcie_init_irq_domain()
405 port->intx_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), PCI_NUM_INTX, in xilinx_cpm_pcie_init_irq_domain()
407 if (!port->intx_domain) in xilinx_cpm_pcie_init_irq_domain()
410 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); in xilinx_cpm_pcie_init_irq_domain()
413 raw_spin_lock_init(&port->lock); in xilinx_cpm_pcie_init_irq_domain()
421 return -ENOMEM; in xilinx_cpm_pcie_init_irq_domain()
426 struct device *dev = port->dev; in xilinx_cpm_setup_irq()
430 port->irq = platform_get_irq(pdev, 0); in xilinx_cpm_setup_irq()
431 if (port->irq < 0) in xilinx_cpm_setup_irq()
432 return port->irq; in xilinx_cpm_setup_irq()
440 irq = irq_create_mapping(port->cpm_domain, i); in xilinx_cpm_setup_irq()
443 return -ENXIO; in xilinx_cpm_setup_irq()
454 port->intx_irq = irq_create_mapping(port->cpm_domain, in xilinx_cpm_setup_irq()
456 if (!port->intx_irq) { in xilinx_cpm_setup_irq()
458 return -ENXIO; in xilinx_cpm_setup_irq()
462 irq_set_chained_handler_and_data(port->intx_irq, in xilinx_cpm_setup_irq()
466 irq_set_chained_handler_and_data(port->irq, in xilinx_cpm_setup_irq()
473 * xilinx_cpm_pcie_init_port - Initialize hardware
478 const struct xilinx_cpm_variant *variant = port->variant; in xilinx_cpm_pcie_init_port()
480 if (variant->version == CPM5NC_HOST) in xilinx_cpm_pcie_init_port()
484 dev_info(port->dev, "PCIe Link is UP\n"); in xilinx_cpm_pcie_init_port()
486 dev_info(port->dev, "PCIe Link is DOWN\n"); in xilinx_cpm_pcie_init_port()
501 writel(variant->ir_misc_value, in xilinx_cpm_pcie_init_port()
502 port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); in xilinx_cpm_pcie_init_port()
504 if (variant->ir_enable) { in xilinx_cpm_pcie_init_port()
506 port->cpm_base + variant->ir_enable); in xilinx_cpm_pcie_init_port()
516 * xilinx_cpm_pcie_parse_dt - Parse Device tree
525 struct device *dev = port->dev; in xilinx_cpm_pcie_parse_dt()
529 port->cpm_base = devm_platform_ioremap_resource_byname(pdev, in xilinx_cpm_pcie_parse_dt()
531 if (IS_ERR(port->cpm_base)) in xilinx_cpm_pcie_parse_dt()
532 return PTR_ERR(port->cpm_base); in xilinx_cpm_pcie_parse_dt()
536 return -ENXIO; in xilinx_cpm_pcie_parse_dt()
538 port->cfg = pci_ecam_create(dev, res, bus_range, in xilinx_cpm_pcie_parse_dt()
540 if (IS_ERR(port->cfg)) in xilinx_cpm_pcie_parse_dt()
541 return PTR_ERR(port->cfg); in xilinx_cpm_pcie_parse_dt()
543 if (port->variant->version == CPM5 || in xilinx_cpm_pcie_parse_dt()
544 port->variant->version == CPM5_HOST1) { in xilinx_cpm_pcie_parse_dt()
545 port->reg_base = devm_platform_ioremap_resource_byname(pdev, in xilinx_cpm_pcie_parse_dt()
547 if (IS_ERR(port->reg_base)) in xilinx_cpm_pcie_parse_dt()
548 return PTR_ERR(port->reg_base); in xilinx_cpm_pcie_parse_dt()
550 port->reg_base = port->cfg->win; in xilinx_cpm_pcie_parse_dt()
558 irq_set_chained_handler_and_data(port->intx_irq, NULL, NULL); in xilinx_cpm_free_interrupts()
559 irq_set_chained_handler_and_data(port->irq, NULL, NULL); in xilinx_cpm_free_interrupts()
563 * xilinx_cpm_pcie_probe - Probe function
571 struct device *dev = &pdev->dev; in xilinx_cpm_pcie_probe()
578 return -ENODEV; in xilinx_cpm_pcie_probe()
582 port->dev = dev; in xilinx_cpm_pcie_probe()
584 port->variant = of_device_get_match_data(dev); in xilinx_cpm_pcie_probe()
586 if (port->variant->version != CPM5NC_HOST) { in xilinx_cpm_pcie_probe()
592 bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); in xilinx_cpm_pcie_probe()
594 err = -ENODEV; in xilinx_cpm_pcie_probe()
598 err = xilinx_cpm_pcie_parse_dt(port, bus->res); in xilinx_cpm_pcie_probe()
606 if (port->variant->version != CPM5NC_HOST) { in xilinx_cpm_pcie_probe()
614 bridge->sysdata = port->cfg; in xilinx_cpm_pcie_probe()
615 bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; in xilinx_cpm_pcie_probe()
624 if (port->variant->version != CPM5NC_HOST) in xilinx_cpm_pcie_probe()
627 pci_ecam_free(port->cfg); in xilinx_cpm_pcie_probe()
629 if (port->variant->version != CPM5NC_HOST) in xilinx_cpm_pcie_probe()
640 .version = CPM5,
659 .compatible = "xlnx,versal-cpm-host-1.00",
663 .compatible = "xlnx,versal-cpm5-host",
667 .compatible = "xlnx,versal-cpm5-host1",
671 .compatible = "xlnx,versal-cpm5nc-host",
679 .name = "xilinx-cpm-pcie",