Lines Matching +full:pcie +full:- +full:host +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas RZ/G3S SoCs
8 * drivers/pci/controller/pcie-rcar-host.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
22 #include <linux/irqchip/irq-msi-lib.h>
64 #define RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA BIT(1)
107 #define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 1)
111 #define RZG3S_PCI_PERM_PIPE_PHY_REG_EN BIT(1)
152 /* PCIe registers */
175 * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
197 * struct rzg3s_pcie_soc_data - SoC specific data
199 * @power_resets: array with the resets that need to be de-asserted after
200 * power-on
201 * @cfg_resets: array with the resets that need to be de-asserted after
207 int (*init_phy)(struct rzg3s_pcie_host *host);
215 * struct rzg3s_pcie_port - RZ/G3S PCIe Root Port data structure
216 * @refclk: PCIe reference clock
227 * struct rzg3s_pcie_host - RZ/G3S PCIe data structure
229 * @pcie: base address for PCIe registers
237 * @port: PCIe Root Port
244 void __iomem *pcie; member
271 static int rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host) in rzg3s_pcie_child_issue_request() argument
276 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS, in rzg3s_pcie_child_issue_request()
279 ret = readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val, in rzg3s_pcie_child_issue_request()
284 return -EIO; in rzg3s_pcie_child_issue_request()
292 struct rzg3s_pcie_host *host = bus->sysdata; in rzg3s_pcie_child_prepare_bus() local
300 writel_relaxed(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) | in rzg3s_pcie_child_prepare_bus()
304 host->axi + RZG3S_PCI_REQADR1); in rzg3s_pcie_child_prepare_bus()
307 writel_relaxed(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE); in rzg3s_pcie_child_prepare_bus()
310 static int rzg3s_pcie_child_read_conf(struct rzg3s_pcie_host *host, in rzg3s_pcie_child_read_conf() argument
314 bool type0 = pci_is_root_bus(bus->parent) ? true : false; in rzg3s_pcie_child_read_conf()
322 host->axi + RZG3S_PCI_REQISS); in rzg3s_pcie_child_read_conf()
325 ret = rzg3s_pcie_child_issue_request(host); in rzg3s_pcie_child_read_conf()
330 *data = readl_relaxed(host->axi + RZG3S_PCI_REQRCVDAT); in rzg3s_pcie_child_read_conf()
339 struct rzg3s_pcie_host *host = bus->sysdata; in rzg3s_pcie_child_read() local
342 ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, val); in rzg3s_pcie_child_read()
347 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in rzg3s_pcie_child_read()
352 static int rzg3s_pcie_child_write_conf(struct rzg3s_pcie_host *host, in rzg3s_pcie_child_write_conf() argument
356 bool type0 = pci_is_root_bus(bus->parent) ? true : false; in rzg3s_pcie_child_write_conf()
362 writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(0)); in rzg3s_pcie_child_write_conf()
363 writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(1)); in rzg3s_pcie_child_write_conf()
364 writel_relaxed(data, host->axi + RZG3S_PCI_REQDATA(2)); in rzg3s_pcie_child_write_conf()
369 host->axi + RZG3S_PCI_REQISS); in rzg3s_pcie_child_write_conf()
372 ret = rzg3s_pcie_child_issue_request(host); in rzg3s_pcie_child_write_conf()
383 struct rzg3s_pcie_host *host = bus->sysdata; in rzg3s_pcie_child_write() local
388 return rzg3s_pcie_child_write_conf(host, bus, devfn, where, val); in rzg3s_pcie_child_write()
393 * example, software may perform a 16-bit write. If the hardware only in rzg3s_pcie_child_write()
394 * supports 32-bit accesses, we must do a 32-bit read, merge in the 16 in rzg3s_pcie_child_write()
395 * bits we intend to write, followed by a 32-bit write. If the 16 bits in rzg3s_pcie_child_write()
397 * (write-one-to-clear) bits set, we just inadvertently cleared in rzg3s_pcie_child_write()
400 if (!bus->unsafe_warn) { in rzg3s_pcie_child_write()
401 …dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1… in rzg3s_pcie_child_write()
402 size, pci_domain_nr(bus), bus->number, in rzg3s_pcie_child_write()
404 bus->unsafe_warn = 1; in rzg3s_pcie_child_write()
407 ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, &data); in rzg3s_pcie_child_write()
411 if (size == 1) { in rzg3s_pcie_child_write()
423 return rzg3s_pcie_child_write_conf(host, bus, devfn, where, data); in rzg3s_pcie_child_write()
434 struct rzg3s_pcie_host *host = bus->sysdata; in rzg3s_pcie_root_map_bus() local
439 return host->pcie + where; in rzg3s_pcie_root_map_bus()
446 struct rzg3s_pcie_host *host = bus->sysdata; in rzg3s_pcie_root_write() local
451 host->axi + RZG3S_PCI_PERM); in rzg3s_pcie_root_write()
456 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); in rzg3s_pcie_root_write()
469 struct rzg3s_pcie_host *host = irq_desc_get_handler_data(desc); in rzg3s_pcie_intx_irq_handler() local
472 u32 intx = irq - host->intx_irqs[0]; in rzg3s_pcie_intx_irq_handler()
475 generic_handle_domain_irq(host->intx_domain, intx); in rzg3s_pcie_intx_irq_handler()
483 struct rzg3s_pcie_host *host = data; in rzg3s_pcie_msi_irq() local
484 struct rzg3s_pcie_msi *msi = &host->msi; in rzg3s_pcie_msi_irq()
488 status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS); in rzg3s_pcie_msi_irq()
493 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, in rzg3s_pcie_msi_irq()
496 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS, in rzg3s_pcie_msi_irq()
500 status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id)); in rzg3s_pcie_msi_irq()
508 ret = generic_handle_domain_irq(msi->domain, bit); in rzg3s_pcie_msi_irq()
515 host->axi + RZG3S_PCI_MSIRS(reg_id)); in rzg3s_pcie_msi_irq()
525 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); in rzg3s_pcie_msi_irq_ack() local
526 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_ack()
527 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_ack()
529 guard(raw_spinlock_irqsave)(&host->hw_lock); in rzg3s_pcie_msi_irq_ack()
531 writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); in rzg3s_pcie_msi_irq_ack()
537 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); in rzg3s_pcie_msi_irq_mask() local
538 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_mask()
539 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_mask()
541 guard(raw_spinlock_irqsave)(&host->hw_lock); in rzg3s_pcie_msi_irq_mask()
543 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), in rzg3s_pcie_msi_irq_mask()
550 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); in rzg3s_pcie_msi_irq_unmask() local
551 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_unmask()
552 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; in rzg3s_pcie_msi_irq_unmask()
554 guard(raw_spinlock_irqsave)(&host->hw_lock); in rzg3s_pcie_msi_irq_unmask()
556 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), in rzg3s_pcie_msi_irq_unmask()
564 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); in rzg3s_pcie_irq_compose_msi_msg() local
571 lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) & in rzg3s_pcie_irq_compose_msi_msg()
573 hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU); in rzg3s_pcie_irq_compose_msi_msg()
575 msg->address_lo = lo; in rzg3s_pcie_irq_compose_msi_msg()
576 msg->address_hi = hi; in rzg3s_pcie_irq_compose_msi_msg()
577 msg->data = data->hwirq; in rzg3s_pcie_irq_compose_msi_msg()
581 .name = "rzg3s-pcie-msi",
592 struct rzg3s_pcie_msi *msi = domain->host_data; in rzg3s_pcie_msi_domain_alloc()
595 scoped_guard(mutex, &msi->map_lock) { in rzg3s_pcie_msi_domain_alloc()
596 hwirq = bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR, in rzg3s_pcie_msi_domain_alloc()
601 return -ENOSPC; in rzg3s_pcie_msi_domain_alloc()
606 domain->host_data, handle_edge_irq, NULL, in rzg3s_pcie_msi_domain_alloc()
617 struct rzg3s_pcie_msi *msi = domain->host_data; in rzg3s_pcie_msi_domain_free()
619 guard(mutex)(&msi->map_lock); in rzg3s_pcie_msi_domain_free()
621 bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs)); in rzg3s_pcie_msi_domain_free()
642 .prefix = "RZG3S-",
648 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); in rzg3s_pcie_msi_allocate_domains() local
649 struct device *dev = host->dev; in rzg3s_pcie_msi_allocate_domains()
657 msi->domain = msi_create_parent_irq_domain(&info, in rzg3s_pcie_msi_allocate_domains()
659 if (!msi->domain) in rzg3s_pcie_msi_allocate_domains()
660 return dev_err_probe(dev, -ENOMEM, in rzg3s_pcie_msi_allocate_domains()
666 static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host) in rzg3s_pcie_msi_hw_setup() argument
669 struct rzg3s_pcie_msi *msi = &host->msi; in rzg3s_pcie_msi_hw_setup()
676 RZG3S_PCI_MSI_INT_NR - 1), in rzg3s_pcie_msi_hw_setup()
677 host->axi + RZG3S_PCI_MSIRCVWMSKL); in rzg3s_pcie_msi_hw_setup()
680 writel_relaxed(upper_32_bits(msi->window_base), in rzg3s_pcie_msi_hw_setup()
681 host->axi + RZG3S_PCI_MSIRCVWADRU); in rzg3s_pcie_msi_hw_setup()
682 writel_relaxed(lower_32_bits(msi->window_base) | in rzg3s_pcie_msi_hw_setup()
685 host->axi + RZG3S_PCI_MSIRCVWADRL); in rzg3s_pcie_msi_hw_setup()
690 host->axi + RZG3S_PCI_MSIRE(reg_id)); in rzg3s_pcie_msi_hw_setup()
695 host->axi + RZG3S_PCI_MSGRCVIE); in rzg3s_pcie_msi_hw_setup()
698 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, in rzg3s_pcie_msi_hw_setup()
705 static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host) in rzg3s_pcie_msi_setup() argument
708 struct rzg3s_pcie_msi *msi = &host->msi; in rzg3s_pcie_msi_setup()
709 struct device *dev = host->dev; in rzg3s_pcie_msi_setup()
712 msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA, 0); in rzg3s_pcie_msi_setup()
713 if (!msi->pages) in rzg3s_pcie_msi_setup()
714 return -ENOMEM; in rzg3s_pcie_msi_setup()
716 msi->dma_addr = dma_map_single(dev, (void *)msi->pages, size * 2, in rzg3s_pcie_msi_setup()
718 if (dma_mapping_error(dev, msi->dma_addr)) { in rzg3s_pcie_msi_setup()
719 ret = -ENOMEM; in rzg3s_pcie_msi_setup()
733 basel = readl_relaxed(host->axi + RZG3S_PCI_AWBASEL(id)); in rzg3s_pcie_msi_setup()
738 baseu = readl_relaxed(host->axi + RZG3S_PCI_AWBASEU(id)); in rzg3s_pcie_msi_setup()
741 maskl = readl_relaxed(host->axi + RZG3S_PCI_AWMASKL(id)); in rzg3s_pcie_msi_setup()
742 masku = readl_relaxed(host->axi + RZG3S_PCI_AWMASKU(id)); in rzg3s_pcie_msi_setup()
745 if (msi->dma_addr < base || msi->dma_addr > base + mask) in rzg3s_pcie_msi_setup()
752 ret = -EINVAL; in rzg3s_pcie_msi_setup()
757 msi->window_base = ALIGN(msi->dma_addr, size); in rzg3s_pcie_msi_setup()
758 if (msi->window_base < msi->dma_addr) { in rzg3s_pcie_msi_setup()
759 ret = -EINVAL; in rzg3s_pcie_msi_setup()
763 rzg3s_pcie_msi_hw_setup(host); in rzg3s_pcie_msi_setup()
768 dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); in rzg3s_pcie_msi_setup()
770 free_pages(msi->pages, 0); in rzg3s_pcie_msi_setup()
774 static void rzg3s_pcie_msi_hw_teardown(struct rzg3s_pcie_host *host) in rzg3s_pcie_msi_hw_teardown() argument
779 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, in rzg3s_pcie_msi_hw_teardown()
783 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE, in rzg3s_pcie_msi_hw_teardown()
788 writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id)); in rzg3s_pcie_msi_hw_teardown()
791 writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL); in rzg3s_pcie_msi_hw_teardown()
794 static void rzg3s_pcie_teardown_msi(struct rzg3s_pcie_host *host) in rzg3s_pcie_teardown_msi() argument
797 struct rzg3s_pcie_msi *msi = &host->msi; in rzg3s_pcie_teardown_msi()
799 rzg3s_pcie_msi_hw_teardown(host); in rzg3s_pcie_teardown_msi()
801 free_irq(msi->irq, host); in rzg3s_pcie_teardown_msi()
802 irq_domain_remove(msi->domain); in rzg3s_pcie_teardown_msi()
805 dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); in rzg3s_pcie_teardown_msi()
806 free_pages(msi->pages, 0); in rzg3s_pcie_teardown_msi()
809 static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host) in rzg3s_pcie_init_msi() argument
811 struct platform_device *pdev = to_platform_device(host->dev); in rzg3s_pcie_init_msi()
812 struct rzg3s_pcie_msi *msi = &host->msi; in rzg3s_pcie_init_msi()
813 struct device *dev = host->dev; in rzg3s_pcie_init_msi()
817 ret = devm_mutex_init(dev, &msi->map_lock); in rzg3s_pcie_init_msi()
821 msi->irq = platform_get_irq_byname(pdev, "msi"); in rzg3s_pcie_init_msi()
822 if (msi->irq < 0) in rzg3s_pcie_init_msi()
823 return dev_err_probe(dev, msi->irq, "Failed to get MSI IRQ!\n"); in rzg3s_pcie_init_msi()
825 devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev)); in rzg3s_pcie_init_msi()
827 return -ENOMEM; in rzg3s_pcie_init_msi()
834 * Don't use devm_request_irq() as the driver uses non-devm helpers in rzg3s_pcie_init_msi()
837 ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host); in rzg3s_pcie_init_msi()
843 ret = rzg3s_pcie_msi_setup(host); in rzg3s_pcie_init_msi()
852 free_irq(msi->irq, host); in rzg3s_pcie_init_msi()
854 irq_domain_remove(msi->domain); in rzg3s_pcie_init_msi()
860 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); in rzg3s_pcie_intx_irq_ack() local
862 guard(raw_spinlock_irqsave)(&host->hw_lock); in rzg3s_pcie_intx_irq_ack()
864 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, in rzg3s_pcie_intx_irq_ack()
865 RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), in rzg3s_pcie_intx_irq_ack()
866 RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); in rzg3s_pcie_intx_irq_ack()
871 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); in rzg3s_pcie_intx_irq_mask() local
873 guard(raw_spinlock_irqsave)(&host->hw_lock); in rzg3s_pcie_intx_irq_mask()
875 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, in rzg3s_pcie_intx_irq_mask()
876 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 0); in rzg3s_pcie_intx_irq_mask()
881 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); in rzg3s_pcie_intx_irq_unmask() local
883 guard(raw_spinlock_irqsave)(&host->hw_lock); in rzg3s_pcie_intx_irq_unmask()
885 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, in rzg3s_pcie_intx_irq_unmask()
886 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), in rzg3s_pcie_intx_irq_unmask()
887 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq)); in rzg3s_pcie_intx_irq_unmask()
891 .name = "PCIe INTx",
902 irq_set_chip_data(irq, domain->host_data); in rzg3s_pcie_intx_map()
912 static int rzg3s_pcie_init_irqdomain(struct rzg3s_pcie_host *host) in rzg3s_pcie_init_irqdomain() argument
914 struct device *dev = host->dev; in rzg3s_pcie_init_irqdomain()
925 return dev_err_probe(dev, -EINVAL, in rzg3s_pcie_init_irqdomain()
929 host->intx_irqs[i] = irq; in rzg3s_pcie_init_irqdomain()
932 host); in rzg3s_pcie_init_irqdomain()
935 host->intx_domain = irq_domain_create_linear(dev_fwnode(dev), in rzg3s_pcie_init_irqdomain()
938 host); in rzg3s_pcie_init_irqdomain()
939 if (!host->intx_domain) in rzg3s_pcie_init_irqdomain()
940 return dev_err_probe(dev, -EINVAL, in rzg3s_pcie_init_irqdomain()
942 irq_domain_update_bus_token(host->intx_domain, DOMAIN_BUS_WIRED); in rzg3s_pcie_init_irqdomain()
945 int ret = rzg3s_pcie_init_msi(host); in rzg3s_pcie_init_irqdomain()
948 irq_domain_remove(host->intx_domain); in rzg3s_pcie_init_irqdomain()
956 static void rzg3s_pcie_teardown_irqdomain(struct rzg3s_pcie_host *host) in rzg3s_pcie_teardown_irqdomain() argument
959 rzg3s_pcie_teardown_msi(host); in rzg3s_pcie_teardown_irqdomain()
961 irq_domain_remove(host->intx_domain); in rzg3s_pcie_teardown_irqdomain()
964 static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) in rzg3s_pcie_set_max_link_speed() argument
978 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, tmp, in rzg3s_pcie_set_max_link_speed()
986 ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA); in rzg3s_pcie_set_max_link_speed()
987 cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); in rzg3s_pcie_set_max_link_speed()
989 switch (pcie_link_speed[host->max_link_speed]) { in rzg3s_pcie_set_max_link_speed()
991 max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0); in rzg3s_pcie_set_max_link_speed()
996 return -EINVAL; in rzg3s_pcie_set_max_link_speed()
1008 if (cur_link_speed == host->max_link_speed || in rzg3s_pcie_set_max_link_speed()
1013 rzg3s_pcie_update_bits(host->pcie, pcie_cap + PCI_EXP_LNKCTL2, in rzg3s_pcie_set_max_link_speed()
1018 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, in rzg3s_pcie_set_max_link_speed()
1023 link_speed - 1)); in rzg3s_pcie_set_max_link_speed()
1025 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT2, cs2, in rzg3s_pcie_set_max_link_speed()
1034 * should be de-asserted after checking for PCI_PCSTAT2_LS_CHG_DONE. in rzg3s_pcie_set_max_link_speed()
1036 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, in rzg3s_pcie_set_max_link_speed()
1042 static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) in rzg3s_pcie_config_init() argument
1044 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); in rzg3s_pcie_config_init()
1051 ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); in rzg3s_pcie_config_init()
1053 return -ENODEV; in rzg3s_pcie_config_init()
1055 bus = ft->res; in rzg3s_pcie_config_init()
1056 primary_bus = bus->start; in rzg3s_pcie_config_init()
1057 secondary_bus = bus->start + 1; in rzg3s_pcie_config_init()
1058 subordinate_bus = bus->end; in rzg3s_pcie_config_init()
1062 host->axi + RZG3S_PCI_PERM); in rzg3s_pcie_config_init()
1065 writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); in rzg3s_pcie_config_init()
1066 writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); in rzg3s_pcie_config_init()
1069 writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS); in rzg3s_pcie_config_init()
1070 writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS); in rzg3s_pcie_config_init()
1071 writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS); in rzg3s_pcie_config_init()
1074 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); in rzg3s_pcie_config_init()
1079 static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host) in rzg3s_pcie_irq_init() argument
1091 host->axi + RZG3S_PCI_PEIS0); in rzg3s_pcie_irq_init()
1094 writel_relaxed(0, host->axi + RZG3S_PCI_PEIE0); in rzg3s_pcie_irq_init()
1097 writel_relaxed(~0U, host->axi + RZG3S_PCI_PEIS1); in rzg3s_pcie_irq_init()
1100 writel_relaxed(0, host->axi + RZG3S_PCI_PEIE1); in rzg3s_pcie_irq_init()
1103 writel_relaxed(~0U, host->axi + RZG3S_PCI_AMEIS); in rzg3s_pcie_irq_init()
1106 writel_relaxed(~0U, host->axi + RZG3S_PCI_ASEIS1); in rzg3s_pcie_irq_init()
1109 writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS); in rzg3s_pcie_irq_init()
1112 static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host) in rzg3s_pcie_power_resets_deassert() argument
1114 const struct rzg3s_pcie_soc_data *data = host->data; in rzg3s_pcie_power_resets_deassert()
1118 * 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from in rzg3s_pcie_power_resets_deassert()
1119 * power on to the de-assertion of reset. in rzg3s_pcie_power_resets_deassert()
1122 return reset_control_bulk_deassert(data->num_power_resets, in rzg3s_pcie_power_resets_deassert()
1123 host->power_resets); in rzg3s_pcie_power_resets_deassert()
1126 static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host) in rzg3s_pcie_resets_prepare_and_get() argument
1128 const struct rzg3s_pcie_soc_data *data = host->data; in rzg3s_pcie_resets_prepare_and_get()
1132 host->power_resets = devm_kmalloc_array(host->dev, in rzg3s_pcie_resets_prepare_and_get()
1133 data->num_power_resets, in rzg3s_pcie_resets_prepare_and_get()
1134 sizeof(*host->power_resets), in rzg3s_pcie_resets_prepare_and_get()
1136 if (!host->power_resets) in rzg3s_pcie_resets_prepare_and_get()
1137 return -ENOMEM; in rzg3s_pcie_resets_prepare_and_get()
1139 for (i = 0; i < data->num_power_resets; i++) in rzg3s_pcie_resets_prepare_and_get()
1140 host->power_resets[i].id = data->power_resets[i]; in rzg3s_pcie_resets_prepare_and_get()
1142 host->cfg_resets = devm_kmalloc_array(host->dev, in rzg3s_pcie_resets_prepare_and_get()
1143 data->num_cfg_resets, in rzg3s_pcie_resets_prepare_and_get()
1144 sizeof(*host->cfg_resets), in rzg3s_pcie_resets_prepare_and_get()
1146 if (!host->cfg_resets) in rzg3s_pcie_resets_prepare_and_get()
1147 return -ENOMEM; in rzg3s_pcie_resets_prepare_and_get()
1149 for (i = 0; i < data->num_cfg_resets; i++) in rzg3s_pcie_resets_prepare_and_get()
1150 host->cfg_resets[i].id = data->cfg_resets[i]; in rzg3s_pcie_resets_prepare_and_get()
1152 ret = devm_reset_control_bulk_get_exclusive(host->dev, in rzg3s_pcie_resets_prepare_and_get()
1153 data->num_power_resets, in rzg3s_pcie_resets_prepare_and_get()
1154 host->power_resets); in rzg3s_pcie_resets_prepare_and_get()
1158 return devm_reset_control_bulk_get_exclusive(host->dev, in rzg3s_pcie_resets_prepare_and_get()
1159 data->num_cfg_resets, in rzg3s_pcie_resets_prepare_and_get()
1160 host->cfg_resets); in rzg3s_pcie_resets_prepare_and_get()
1163 static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host) in rzg3s_pcie_host_parse_port() argument
1165 struct device_node *of_port = of_get_next_child(host->dev->of_node, NULL); in rzg3s_pcie_host_parse_port()
1166 struct rzg3s_pcie_port *port = &host->port; in rzg3s_pcie_host_parse_port()
1169 ret = of_property_read_u32(of_port, "vendor-id", &port->vendor_id); in rzg3s_pcie_host_parse_port()
1173 ret = of_property_read_u32(of_port, "device-id", &port->device_id); in rzg3s_pcie_host_parse_port()
1177 port->refclk = of_clk_get_by_name(of_port, "ref"); in rzg3s_pcie_host_parse_port()
1178 if (IS_ERR(port->refclk)) in rzg3s_pcie_host_parse_port()
1179 return PTR_ERR(port->refclk); in rzg3s_pcie_host_parse_port()
1184 static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host) in rzg3s_pcie_host_init_port() argument
1186 struct rzg3s_pcie_port *port = &host->port; in rzg3s_pcie_host_init_port()
1187 struct device *dev = host->dev; in rzg3s_pcie_host_init_port()
1192 host->axi + RZG3S_PCI_PERM); in rzg3s_pcie_host_init_port()
1195 writew_relaxed(port->vendor_id, host->pcie + PCI_VENDOR_ID); in rzg3s_pcie_host_init_port()
1196 writew_relaxed(port->device_id, host->pcie + PCI_DEVICE_ID); in rzg3s_pcie_host_init_port()
1199 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); in rzg3s_pcie_host_init_port()
1201 ret = clk_prepare_enable(port->refclk); in rzg3s_pcie_host_init_port()
1206 if (host->data->init_phy) { in rzg3s_pcie_host_init_port()
1207 ret = host->data->init_phy(host); in rzg3s_pcie_host_init_port()
1217 clk_disable_unprepare(port->refclk); in rzg3s_pcie_host_init_port()
1221 static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host) in rzg3s_pcie_host_init() argument
1226 /* Initialize the PCIe related registers */ in rzg3s_pcie_host_init()
1227 ret = rzg3s_pcie_config_init(host); in rzg3s_pcie_host_init()
1231 ret = rzg3s_pcie_host_init_port(host); in rzg3s_pcie_host_init()
1236 rzg3s_pcie_irq_init(host); in rzg3s_pcie_host_init()
1238 ret = reset_control_bulk_deassert(host->data->num_cfg_resets, in rzg3s_pcie_host_init()
1239 host->cfg_resets); in rzg3s_pcie_host_init()
1244 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val, in rzg3s_pcie_host_init()
1252 val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); in rzg3s_pcie_host_init()
1253 dev_info(host->dev, "PCIe link status [0x%x]\n", val); in rzg3s_pcie_host_init()
1258 reset_control_bulk_assert(host->data->num_cfg_resets, in rzg3s_pcie_host_init()
1259 host->cfg_resets); in rzg3s_pcie_host_init()
1261 clk_disable_unprepare(host->port.refclk); in rzg3s_pcie_host_init()
1265 static void rzg3s_pcie_set_inbound_window(struct rzg3s_pcie_host *host, in rzg3s_pcie_set_inbound_window() argument
1271 host->axi + RZG3S_PCI_ADESTU(id)); in rzg3s_pcie_set_inbound_window()
1273 host->axi + RZG3S_PCI_ADESTL(id)); in rzg3s_pcie_set_inbound_window()
1276 writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id)); in rzg3s_pcie_set_inbound_window()
1277 writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id)); in rzg3s_pcie_set_inbound_window()
1279 /* Set PCIe window base address and enable the window */ in rzg3s_pcie_set_inbound_window()
1281 host->axi + RZG3S_PCI_AWBASEU(id)); in rzg3s_pcie_set_inbound_window()
1283 host->axi + RZG3S_PCI_AWBASEL(id)); in rzg3s_pcie_set_inbound_window()
1286 static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host, in rzg3s_pcie_set_inbound_windows() argument
1290 u64 pci_addr = entry->res->start - entry->offset; in rzg3s_pcie_set_inbound_windows()
1291 u64 cpu_addr = entry->res->start; in rzg3s_pcie_set_inbound_windows()
1292 u64 cpu_end = entry->res->end; in rzg3s_pcie_set_inbound_windows()
1299 return dev_err_probe(host->dev, -ENOSPC, in rzg3s_pcie_set_inbound_windows()
1301 entry->res->name); in rzg3s_pcie_set_inbound_windows()
1303 size = resource_size(entry->res) - size_id; in rzg3s_pcie_set_inbound_windows()
1314 * - 34.3.1.69 AXI Window Base (Lower) Registers in rzg3s_pcie_set_inbound_windows()
1315 * - 34.3.1.71 AXI Window Mask (Lower) Registers in rzg3s_pcie_set_inbound_windows()
1316 * - 34.3.1.73 AXI Destination (Lower) Registers) in rzg3s_pcie_set_inbound_windows()
1317 * the CPU addr, PCIe addr, size should be 4K aligned and be a in rzg3s_pcie_set_inbound_windows()
1329 * 12 LSB bits to be 0xfff. Subtract 1 from size for this. in rzg3s_pcie_set_inbound_windows()
1331 rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr, in rzg3s_pcie_set_inbound_windows()
1332 size - 1, id); in rzg3s_pcie_set_inbound_windows()
1344 static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host) in rzg3s_pcie_parse_map_dma_ranges() argument
1346 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); in rzg3s_pcie_parse_map_dma_ranges()
1350 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in rzg3s_pcie_parse_map_dma_ranges()
1351 ret = rzg3s_pcie_set_inbound_windows(host, entry, &i); in rzg3s_pcie_parse_map_dma_ranges()
1359 static void rzg3s_pcie_set_outbound_window(struct rzg3s_pcie_host *host, in rzg3s_pcie_set_outbound_window() argument
1362 struct resource *res = win->res; in rzg3s_pcie_set_outbound_window()
1366 if (res->flags & IORESOURCE_IO) in rzg3s_pcie_set_outbound_window()
1367 res_start = pci_pio_to_address(res->start) - win->offset; in rzg3s_pcie_set_outbound_window()
1369 res_start = res->start - win->offset; in rzg3s_pcie_set_outbound_window()
1372 * According to the RZ/G3S HW manual (Rev.1.10, section 34.3.1.75 PCIe in rzg3s_pcie_set_outbound_window()
1379 size = roundup_pow_of_two(size) - 1; in rzg3s_pcie_set_outbound_window()
1381 /* Set PCIe destination */ in rzg3s_pcie_set_outbound_window()
1383 host->axi + RZG3S_PCI_PDESTU(id)); in rzg3s_pcie_set_outbound_window()
1385 host->axi + RZG3S_PCI_PDESTL(id)); in rzg3s_pcie_set_outbound_window()
1387 /* Set PCIe window mask */ in rzg3s_pcie_set_outbound_window()
1388 writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id)); in rzg3s_pcie_set_outbound_window()
1389 writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id)); in rzg3s_pcie_set_outbound_window()
1391 /* Set PCIe window base and enable the window */ in rzg3s_pcie_set_outbound_window()
1393 host->axi + RZG3S_PCI_PWBASEU(id)); in rzg3s_pcie_set_outbound_window()
1395 host->axi + RZG3S_PCI_PWBASEL(id)); in rzg3s_pcie_set_outbound_window()
1398 static int rzg3s_pcie_parse_map_ranges(struct rzg3s_pcie_host *host) in rzg3s_pcie_parse_map_ranges() argument
1400 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); in rzg3s_pcie_parse_map_ranges()
1404 resource_list_for_each_entry(win, &bridge->windows) { in rzg3s_pcie_parse_map_ranges()
1405 struct resource *res = win->res; in rzg3s_pcie_parse_map_ranges()
1408 return dev_err_probe(host->dev, -ENOSPC, in rzg3s_pcie_parse_map_ranges()
1410 res->name); in rzg3s_pcie_parse_map_ranges()
1412 if (!res->flags) in rzg3s_pcie_parse_map_ranges()
1418 rzg3s_pcie_set_outbound_window(host, win, i); in rzg3s_pcie_parse_map_ranges()
1427 static int rzg3s_soc_pcie_init_phy(struct rzg3s_pcie_host *host) in rzg3s_soc_pcie_init_phy() argument
1455 host->axi + RZG3S_PCI_PERM); in rzg3s_soc_pcie_init_phy()
1459 host->axi + RZG3S_PCI_PHY_XCFGD(i)); in rzg3s_soc_pcie_init_phy()
1464 host->axi + RZG3S_PCI_PHY_XCFGA_CMN(i)); in rzg3s_soc_pcie_init_phy()
1469 host->axi + RZG3S_PCI_PHY_XCFGA_RX(i)); in rzg3s_soc_pcie_init_phy()
1472 writel_relaxed(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX); in rzg3s_soc_pcie_init_phy()
1476 host->axi + RZG3S_PCI_PHY_XCFG_CTRL); in rzg3s_soc_pcie_init_phy()
1482 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); in rzg3s_soc_pcie_init_phy()
1488 rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, in rzg3s_pcie_host_setup() argument
1489 int (*init_irqdomain)(struct rzg3s_pcie_host *host), in rzg3s_pcie_host_setup() argument
1490 void (*teardown_irqdomain)(struct rzg3s_pcie_host *host)) in rzg3s_pcie_host_setup() argument
1492 struct device *dev = host->dev; in rzg3s_pcie_host_setup()
1496 ret = rzg3s_pcie_parse_map_dma_ranges(host); in rzg3s_pcie_host_setup()
1502 ret = rzg3s_pcie_parse_map_ranges(host); in rzg3s_pcie_host_setup()
1507 ret = init_irqdomain(host); in rzg3s_pcie_host_setup()
1511 ret = rzg3s_pcie_host_init(host); in rzg3s_pcie_host_setup()
1517 ret = rzg3s_pcie_set_max_link_speed(host); in rzg3s_pcie_host_setup()
1526 teardown_irqdomain(host); in rzg3s_pcie_host_setup()
1534 struct device *dev = &pdev->dev; in rzg3s_pcie_probe()
1535 struct device_node *np = dev->of_node; in rzg3s_pcie_probe()
1538 struct rzg3s_pcie_host *host; in rzg3s_pcie_probe() local
1541 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); in rzg3s_pcie_probe()
1543 return -ENOMEM; in rzg3s_pcie_probe()
1545 host = pci_host_bridge_priv(bridge); in rzg3s_pcie_probe()
1546 host->dev = dev; in rzg3s_pcie_probe()
1547 host->data = device_get_match_data(dev); in rzg3s_pcie_probe()
1548 platform_set_drvdata(pdev, host); in rzg3s_pcie_probe()
1550 host->axi = devm_platform_ioremap_resource(pdev, 0); in rzg3s_pcie_probe()
1551 if (IS_ERR(host->axi)) in rzg3s_pcie_probe()
1552 return PTR_ERR(host->axi); in rzg3s_pcie_probe()
1553 host->pcie = host->axi + RZG3S_PCI_CFG_BASE; in rzg3s_pcie_probe()
1555 host->max_link_speed = of_pci_get_max_link_speed(np); in rzg3s_pcie_probe()
1556 if (host->max_link_speed < 0) in rzg3s_pcie_probe()
1557 host->max_link_speed = 2; in rzg3s_pcie_probe()
1559 ret = rzg3s_pcie_host_parse_port(host); in rzg3s_pcie_probe()
1563 host->sysc = syscon_node_to_regmap(sysc_np); in rzg3s_pcie_probe()
1564 if (IS_ERR(host->sysc)) { in rzg3s_pcie_probe()
1565 ret = PTR_ERR(host->sysc); in rzg3s_pcie_probe()
1569 ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, in rzg3s_pcie_probe()
1571 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); in rzg3s_pcie_probe()
1575 ret = rzg3s_pcie_resets_prepare_and_get(host); in rzg3s_pcie_probe()
1579 ret = rzg3s_pcie_power_resets_deassert(host); in rzg3s_pcie_probe()
1593 raw_spin_lock_init(&host->hw_lock); in rzg3s_pcie_probe()
1595 ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain, in rzg3s_pcie_probe()
1600 bridge->sysdata = host; in rzg3s_pcie_probe()
1601 bridge->ops = &rzg3s_pcie_root_ops; in rzg3s_pcie_probe()
1602 bridge->child_ops = &rzg3s_pcie_child_ops; in rzg3s_pcie_probe()
1610 rzg3s_pcie_teardown_irqdomain(host); in rzg3s_pcie_probe()
1611 reset_control_bulk_deassert(host->data->num_cfg_resets, in rzg3s_pcie_probe()
1612 host->cfg_resets); in rzg3s_pcie_probe()
1617 reset_control_bulk_assert(host->data->num_power_resets, in rzg3s_pcie_probe()
1618 host->power_resets); in rzg3s_pcie_probe()
1624 regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, in rzg3s_pcie_probe()
1628 clk_put(host->port.refclk); in rzg3s_pcie_probe()
1635 struct rzg3s_pcie_host *host = dev_get_drvdata(dev); in rzg3s_pcie_suspend_noirq() local
1636 const struct rzg3s_pcie_soc_data *data = host->data; in rzg3s_pcie_suspend_noirq()
1637 struct rzg3s_pcie_port *port = &host->port; in rzg3s_pcie_suspend_noirq()
1638 struct regmap *sysc = host->sysc; in rzg3s_pcie_suspend_noirq()
1645 clk_disable_unprepare(port->refclk); in rzg3s_pcie_suspend_noirq()
1647 ret = reset_control_bulk_assert(data->num_power_resets, in rzg3s_pcie_suspend_noirq()
1648 host->power_resets); in rzg3s_pcie_suspend_noirq()
1652 ret = reset_control_bulk_assert(data->num_cfg_resets, in rzg3s_pcie_suspend_noirq()
1653 host->cfg_resets); in rzg3s_pcie_suspend_noirq()
1667 reset_control_bulk_deassert(data->num_cfg_resets, in rzg3s_pcie_suspend_noirq()
1668 host->cfg_resets); in rzg3s_pcie_suspend_noirq()
1670 reset_control_bulk_deassert(data->num_power_resets, in rzg3s_pcie_suspend_noirq()
1671 host->power_resets); in rzg3s_pcie_suspend_noirq()
1673 clk_prepare_enable(port->refclk); in rzg3s_pcie_suspend_noirq()
1680 struct rzg3s_pcie_host *host = dev_get_drvdata(dev); in rzg3s_pcie_resume_noirq() local
1681 const struct rzg3s_pcie_soc_data *data = host->data; in rzg3s_pcie_resume_noirq()
1682 struct regmap *sysc = host->sysc; in rzg3s_pcie_resume_noirq()
1687 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); in rzg3s_pcie_resume_noirq()
1691 ret = rzg3s_pcie_power_resets_deassert(host); in rzg3s_pcie_resume_noirq()
1699 ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_msi_hw_setup, in rzg3s_pcie_resume_noirq()
1713 reset_control_bulk_assert(data->num_power_resets, in rzg3s_pcie_resume_noirq()
1714 host->power_resets); in rzg3s_pcie_resume_noirq()
1745 .compatible = "renesas,r9a08g045-pcie",
1753 .name = "rzg3s-pcie-host",