Lines Matching +full:pcie +full:- +full:phy +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
28 #include <linux/phy/phy.h>
35 /* MediaTek-specific configuration registers */
40 /* Host-PCI bridge registers */
48 /* PCIe RC control registers */
67 * struct mt7621_pcie_port - PCIe port information
70 * @pcie: pointer to PCIe host info
72 * @phy: pointer to PHY control block
81 struct mt7621_pcie *pcie; member
83 struct phy *phy; member
91 * struct mt7621_pcie - PCIe host information
93 * @dev: Pointer to PCIe device
94 * @ports: pointer to PCIe port information
105 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) in pcie_read() argument
107 return readl_relaxed(pcie->base + reg); in pcie_read()
110 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
112 writel_relaxed(val, pcie->base + reg); in pcie_write()
117 return readl_relaxed(port->base + reg); in pcie_port_read()
123 writel_relaxed(val, port->base + reg); in pcie_port_write()
129 struct mt7621_pcie *pcie = bus->sysdata; in mt7621_pcie_map_bus() local
130 u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn), in mt7621_pcie_map_bus()
133 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); in mt7621_pcie_map_bus()
135 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); in mt7621_pcie_map_bus()
144 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) in read_config() argument
148 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); in read_config()
149 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); in read_config()
152 static void write_config(struct mt7621_pcie *pcie, unsigned int dev, in write_config() argument
157 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); in write_config()
158 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); in write_config()
163 if (port->gpio_rst) in mt7621_rst_gpio_pcie_assert()
164 gpiod_set_value(port->gpio_rst, 1); in mt7621_rst_gpio_pcie_assert()
169 if (port->gpio_rst) in mt7621_rst_gpio_pcie_deassert()
170 gpiod_set_value(port->gpio_rst, 0); in mt7621_rst_gpio_pcie_deassert()
180 struct mt7621_pcie *pcie = port->pcie; in mt7621_control_assert() local
182 if (pcie->resets_inverted) in mt7621_control_assert()
183 reset_control_assert(port->pcie_rst); in mt7621_control_assert()
185 reset_control_deassert(port->pcie_rst); in mt7621_control_assert()
190 struct mt7621_pcie *pcie = port->pcie; in mt7621_control_deassert() local
192 if (pcie->resets_inverted) in mt7621_control_deassert()
193 reset_control_deassert(port->pcie_rst); in mt7621_control_deassert()
195 reset_control_assert(port->pcie_rst); in mt7621_control_deassert()
198 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie, in mt7621_pcie_parse_port() argument
203 struct device *dev = pcie->dev; in mt7621_pcie_parse_port()
210 return -ENOMEM; in mt7621_pcie_parse_port()
212 port->base = devm_platform_ioremap_resource(pdev, slot + 1); in mt7621_pcie_parse_port()
213 if (IS_ERR(port->base)) in mt7621_pcie_parse_port()
214 return PTR_ERR(port->base); in mt7621_pcie_parse_port()
216 port->clk = devm_get_clk_from_child(dev, node, NULL); in mt7621_pcie_parse_port()
217 if (IS_ERR(port->clk)) { in mt7621_pcie_parse_port()
218 dev_err(dev, "failed to get pcie%d clock\n", slot); in mt7621_pcie_parse_port()
219 return PTR_ERR(port->clk); in mt7621_pcie_parse_port()
222 port->pcie_rst = of_reset_control_get_exclusive(node, NULL); in mt7621_pcie_parse_port()
223 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) { in mt7621_pcie_parse_port()
224 dev_err(dev, "failed to get pcie%d reset control\n", slot); in mt7621_pcie_parse_port()
225 return PTR_ERR(port->pcie_rst); in mt7621_pcie_parse_port()
228 snprintf(name, sizeof(name), "pcie-phy%d", slot); in mt7621_pcie_parse_port()
229 port->phy = devm_of_phy_get(dev, node, name); in mt7621_pcie_parse_port()
230 if (IS_ERR(port->phy)) { in mt7621_pcie_parse_port()
231 dev_err(dev, "failed to get pcie-phy%d\n", slot); in mt7621_pcie_parse_port()
232 err = PTR_ERR(port->phy); in mt7621_pcie_parse_port()
236 port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot, in mt7621_pcie_parse_port()
238 if (IS_ERR(port->gpio_rst)) { in mt7621_pcie_parse_port()
239 dev_err(dev, "failed to get GPIO for PCIe%d\n", slot); in mt7621_pcie_parse_port()
240 err = PTR_ERR(port->gpio_rst); in mt7621_pcie_parse_port()
244 port->slot = slot; in mt7621_pcie_parse_port()
245 port->pcie = pcie; in mt7621_pcie_parse_port()
247 INIT_LIST_HEAD(&port->list); in mt7621_pcie_parse_port()
248 list_add_tail(&port->list, &pcie->ports); in mt7621_pcie_parse_port()
253 reset_control_put(port->pcie_rst); in mt7621_pcie_parse_port()
257 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie) in mt7621_pcie_parse_dt() argument
259 struct device *dev = pcie->dev; in mt7621_pcie_parse_dt()
261 struct device_node *node = dev->of_node, *child; in mt7621_pcie_parse_dt()
264 pcie->base = devm_platform_ioremap_resource(pdev, 0); in mt7621_pcie_parse_dt()
265 if (IS_ERR(pcie->base)) in mt7621_pcie_parse_dt()
266 return PTR_ERR(pcie->base); in mt7621_pcie_parse_dt()
280 err = mt7621_pcie_parse_port(pcie, child, slot); in mt7621_pcie_parse_dt()
292 struct mt7621_pcie *pcie = port->pcie; in mt7621_pcie_init_port() local
293 struct device *dev = pcie->dev; in mt7621_pcie_init_port()
294 u32 slot = port->slot; in mt7621_pcie_init_port()
297 err = phy_init(port->phy); in mt7621_pcie_init_port()
299 dev_err(dev, "failed to initialize port%d phy\n", slot); in mt7621_pcie_init_port()
303 err = phy_power_on(port->phy); in mt7621_pcie_init_port()
305 dev_err(dev, "failed to power on port%d phy\n", slot); in mt7621_pcie_init_port()
306 phy_exit(port->phy); in mt7621_pcie_init_port()
310 port->enabled = true; in mt7621_pcie_init_port()
315 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie) in mt7621_pcie_reset_assert() argument
319 list_for_each_entry(port, &pcie->ports, list) { in mt7621_pcie_reset_assert()
320 /* PCIe RC reset assert */ in mt7621_pcie_reset_assert()
323 /* PCIe EP reset assert */ in mt7621_pcie_reset_assert()
330 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie) in mt7621_pcie_reset_rc_deassert() argument
334 list_for_each_entry(port, &pcie->ports, list) in mt7621_pcie_reset_rc_deassert()
338 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie) in mt7621_pcie_reset_ep_deassert() argument
342 list_for_each_entry(port, &pcie->ports, list) in mt7621_pcie_reset_ep_deassert()
348 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie) in mt7621_pcie_init_ports() argument
350 struct device *dev = pcie->dev; in mt7621_pcie_init_ports()
355 mt7621_pcie_reset_assert(pcie); in mt7621_pcie_init_ports()
356 mt7621_pcie_reset_rc_deassert(pcie); in mt7621_pcie_init_ports()
358 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mt7621_pcie_init_ports()
359 u32 slot = port->slot; in mt7621_pcie_init_ports()
361 if (slot == 1) { in mt7621_pcie_init_ports()
362 port->enabled = true; in mt7621_pcie_init_ports()
369 list_del(&port->list); in mt7621_pcie_init_ports()
374 mt7621_pcie_reset_ep_deassert(pcie); in mt7621_pcie_init_ports()
377 list_for_each_entry(port, &pcie->ports, list) { in mt7621_pcie_init_ports()
378 u32 slot = port->slot; in mt7621_pcie_init_ports()
381 dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n", in mt7621_pcie_init_ports()
384 port->enabled = false; in mt7621_pcie_init_ports()
392 if (slot == 1 && tmp && !tmp->enabled) in mt7621_pcie_init_ports()
393 phy_power_off(tmp->phy); in mt7621_pcie_init_ports()
397 return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV; in mt7621_pcie_init_ports()
402 struct mt7621_pcie *pcie = port->pcie; in mt7621_pcie_enable_port() local
403 u32 slot = port->slot; in mt7621_pcie_enable_port()
406 /* enable pcie interrupt */ in mt7621_pcie_enable_port()
407 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR); in mt7621_pcie_enable_port()
409 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); in mt7621_pcie_enable_port()
420 val = read_config(pcie, slot, PCIE_FTS_NUM); in mt7621_pcie_enable_port()
423 write_config(pcie, slot, PCIE_FTS_NUM, val); in mt7621_pcie_enable_port()
428 struct mt7621_pcie *pcie = pci_host_bridge_priv(host); in mt7621_pcie_enable_ports() local
429 struct device *dev = pcie->dev; in mt7621_pcie_enable_ports()
434 entry = resource_list_first_type(&host->windows, IORESOURCE_IO); in mt7621_pcie_enable_ports()
437 return -EINVAL; in mt7621_pcie_enable_ports()
441 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE); in mt7621_pcie_enable_ports()
442 pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE); in mt7621_pcie_enable_ports()
444 list_for_each_entry(port, &pcie->ports, list) { in mt7621_pcie_enable_ports()
445 if (port->enabled) { in mt7621_pcie_enable_ports()
446 err = clk_prepare_enable(port->clk); in mt7621_pcie_enable_ports()
448 dev_err(dev, "enabling clk pcie%d\n", in mt7621_pcie_enable_ports()
449 port->slot); in mt7621_pcie_enable_ports()
454 dev_info(dev, "PCIE%d enabled\n", port->slot); in mt7621_pcie_enable_ports()
463 struct mt7621_pcie *pcie = pci_host_bridge_priv(host); in mt7621_pcie_register_host() local
465 host->ops = &mt7621_pcie_ops; in mt7621_pcie_register_host()
466 host->sysdata = pcie; in mt7621_pcie_register_host()
477 struct device *dev = &pdev->dev; in mt7621_pcie_probe()
480 struct mt7621_pcie *pcie; in mt7621_pcie_probe() local
484 if (!dev->of_node) in mt7621_pcie_probe()
485 return -ENODEV; in mt7621_pcie_probe()
487 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in mt7621_pcie_probe()
489 return -ENOMEM; in mt7621_pcie_probe()
491 pcie = pci_host_bridge_priv(bridge); in mt7621_pcie_probe()
492 pcie->dev = dev; in mt7621_pcie_probe()
493 platform_set_drvdata(pdev, pcie); in mt7621_pcie_probe()
494 INIT_LIST_HEAD(&pcie->ports); in mt7621_pcie_probe()
498 pcie->resets_inverted = true; in mt7621_pcie_probe()
500 err = mt7621_pcie_parse_dt(pcie); in mt7621_pcie_probe()
506 err = mt7621_pcie_init_ports(pcie); in mt7621_pcie_probe()
514 dev_err(dev, "error enabling pcie ports\n"); in mt7621_pcie_probe()
521 list_for_each_entry(port, &pcie->ports, list) in mt7621_pcie_probe()
522 reset_control_put(port->pcie_rst); in mt7621_pcie_probe()
529 struct mt7621_pcie *pcie = platform_get_drvdata(pdev); in mt7621_pcie_remove() local
532 list_for_each_entry(port, &pcie->ports, list) in mt7621_pcie_remove()
533 reset_control_put(port->pcie_rst); in mt7621_pcie_remove()
537 { .compatible = "mediatek,mt7621-pci" },
546 .name = "mt7621-pci",
552 MODULE_DESCRIPTION("MediaTek MT7621 PCIe host controller driver");