Lines Matching +full:pcie +full:- +full:host +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
11 #include <linux/clk-provider.h>
15 #include <linux/irqchip/irq-msi-lib.h>
61 #define PCIE_PHY_RSTB BIT(1)
79 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
83 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
87 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
112 #define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
124 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
127 #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
136 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
152 * struct mtk_gen3_pcie_pdata - differentiate between host generations
153 * @power_up: pcie power_up callback
156 * @flags: pcie device flags.
159 int (*power_up)(struct mtk_gen3_pcie *pcie);
169 * struct mtk_msi_set - MSI information for each set
181 * struct mtk_gen3_pcie - PCIe port information
182 * @dev: pointer to PCIe device
188 * @clks: PCIe clocks
189 * @num_clks: PCIe clocks count for this port
190 * @max_link_speed: Maximum link speed (PCIe Gen) for this port
191 * @num_lanes: Number of PCIe lanes for this port
192 * @irq: PCIe controller interrupt number
200 * @soc: pointer to SoC-dependent operations
258 * mtk_pcie_config_tlp_header() - Configure a configuration TLP header
269 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header() local
273 bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); in mtk_pcie_config_tlp_header()
276 PCIE_CFG_HEADER(bus->number, devfn); in mtk_pcie_config_tlp_header()
278 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); in mtk_pcie_config_tlp_header()
284 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
286 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; in mtk_pcie_map_bus()
314 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, in mtk_pcie_set_trans_table() argument
329 table_size = BIT(fls(remaining) - 1); in mtk_pcie_set_trans_table()
332 addr_align = BIT(ffs(cpu_addr) - 1); in mtk_pcie_set_trans_table()
338 dev_err(pcie->dev, "illegal table size %#llx\n", in mtk_pcie_set_trans_table()
340 return -EINVAL; in mtk_pcie_set_trans_table()
343 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET; in mtk_pcie_set_trans_table()
344 writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(table_size) - 1), table); in mtk_pcie_set_trans_table()
359 dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", in mtk_pcie_set_trans_table()
366 remaining -= table_size; in mtk_pcie_set_trans_table()
371 dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", in mtk_pcie_set_trans_table()
377 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) in mtk_pcie_enable_msi() argument
383 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_enable_msi()
385 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + in mtk_pcie_enable_msi()
387 msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG + in mtk_pcie_enable_msi()
391 writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); in mtk_pcie_enable_msi()
392 writel_relaxed(upper_32_bits(msi_set->msg_addr), in mtk_pcie_enable_msi()
393 pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + in mtk_pcie_enable_msi()
397 val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); in mtk_pcie_enable_msi()
399 writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); in mtk_pcie_enable_msi()
401 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_enable_msi()
403 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_enable_msi()
406 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) in mtk_pcie_startup_port() argument
409 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_startup_port() local
414 /* Set as RC mode and set controller PCIe Gen speed restriction, if any */ in mtk_pcie_startup_port()
415 val = readl_relaxed(pcie->base + PCIE_SETTING_REG); in mtk_pcie_startup_port()
417 if (pcie->max_link_speed) { in mtk_pcie_startup_port()
421 if (pcie->max_link_speed >= 2) in mtk_pcie_startup_port()
423 GENMASK(pcie->max_link_speed - 2, 0)); in mtk_pcie_startup_port()
425 if (pcie->num_lanes) { in mtk_pcie_startup_port()
429 if (pcie->num_lanes > 1) in mtk_pcie_startup_port()
431 GENMASK(fls(pcie->num_lanes >> 2), 0)); in mtk_pcie_startup_port()
433 writel_relaxed(val, pcie->base + PCIE_SETTING_REG); in mtk_pcie_startup_port()
436 if (pcie->max_link_speed) { in mtk_pcie_startup_port()
437 val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS); in mtk_pcie_startup_port()
439 val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed); in mtk_pcie_startup_port()
440 writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS); in mtk_pcie_startup_port()
444 if (pcie->soc->sys_clk_rdy_time_us) { in mtk_pcie_startup_port()
445 val = readl_relaxed(pcie->base + PCIE_RESOURCE_CTRL_REG); in mtk_pcie_startup_port()
447 pcie->soc->sys_clk_rdy_time_us); in mtk_pcie_startup_port()
448 writel_relaxed(val, pcie->base + PCIE_RESOURCE_CTRL_REG); in mtk_pcie_startup_port()
452 val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1); in mtk_pcie_startup_port()
455 writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1); in mtk_pcie_startup_port()
458 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_startup_port()
460 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_startup_port()
463 val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG); in mtk_pcie_startup_port()
465 writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); in mtk_pcie_startup_port()
469 * causing occasional PCIe link down. In order to overcome the issue, in mtk_pcie_startup_port()
471 * PCIe block is reset using en7523_reset_assert() and in mtk_pcie_startup_port()
474 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { in mtk_pcie_startup_port()
476 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_startup_port()
479 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_startup_port()
482 * Described in PCIe CEM specification revision 6.0. in mtk_pcie_startup_port()
489 /* De-assert reset signals */ in mtk_pcie_startup_port()
492 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_startup_port()
496 err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, in mtk_pcie_startup_port()
503 val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG); in mtk_pcie_startup_port()
507 dev_err(pcie->dev, in mtk_pcie_startup_port()
508 "PCIe link down, current LTSSM state: %s (%#x)\n", in mtk_pcie_startup_port()
513 mtk_pcie_enable_msi(pcie); in mtk_pcie_startup_port()
515 /* Set PCIe translation windows */ in mtk_pcie_startup_port()
516 resource_list_for_each_entry(entry, &host->windows) { in mtk_pcie_startup_port()
517 struct resource *res = entry->res; in mtk_pcie_startup_port()
524 cpu_addr = pci_pio_to_address(res->start); in mtk_pcie_startup_port()
526 cpu_addr = res->start; in mtk_pcie_startup_port()
530 pci_addr = res->start - entry->offset; in mtk_pcie_startup_port()
532 err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, in mtk_pcie_startup_port()
555 .prefix = "MTK3-",
562 struct mtk_gen3_pcie *pcie = data->domain->host_data; in mtk_compose_msi_msg() local
565 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; in mtk_compose_msi_msg()
567 msg->address_hi = upper_32_bits(msi_set->msg_addr); in mtk_compose_msi_msg()
568 msg->address_lo = lower_32_bits(msi_set->msg_addr); in mtk_compose_msi_msg()
569 msg->data = hwirq; in mtk_compose_msi_msg()
570 dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", in mtk_compose_msi_msg()
571 hwirq, msg->address_hi, msg->address_lo, msg->data); in mtk_compose_msi_msg()
579 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; in mtk_msi_bottom_irq_ack()
581 writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET); in mtk_msi_bottom_irq_ack()
587 struct mtk_gen3_pcie *pcie = data->domain->host_data; in mtk_msi_bottom_irq_mask() local
591 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; in mtk_msi_bottom_irq_mask()
593 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_mask()
594 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); in mtk_msi_bottom_irq_mask()
596 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); in mtk_msi_bottom_irq_mask()
597 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_mask()
603 struct mtk_gen3_pcie *pcie = data->domain->host_data; in mtk_msi_bottom_irq_unmask() local
607 hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; in mtk_msi_bottom_irq_unmask()
609 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_unmask()
610 val = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); in mtk_msi_bottom_irq_unmask()
612 writel_relaxed(val, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); in mtk_msi_bottom_irq_unmask()
613 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_msi_bottom_irq_unmask()
628 struct mtk_gen3_pcie *pcie = domain->host_data; in mtk_msi_bottom_domain_alloc() local
632 mutex_lock(&pcie->lock); in mtk_msi_bottom_domain_alloc()
634 hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM, in mtk_msi_bottom_domain_alloc()
637 mutex_unlock(&pcie->lock); in mtk_msi_bottom_domain_alloc()
640 return -ENOSPC; in mtk_msi_bottom_domain_alloc()
643 msi_set = &pcie->msi_sets[set_idx]; in mtk_msi_bottom_domain_alloc()
656 struct mtk_gen3_pcie *pcie = domain->host_data; in mtk_msi_bottom_domain_free() local
659 mutex_lock(&pcie->lock); in mtk_msi_bottom_domain_free()
661 bitmap_release_region(pcie->msi_irq_in_use, data->hwirq, in mtk_msi_bottom_domain_free()
664 mutex_unlock(&pcie->lock); in mtk_msi_bottom_domain_free()
676 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); in mtk_intx_mask() local
680 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_intx_mask()
681 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_mask()
682 val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); in mtk_intx_mask()
683 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_mask()
684 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_intx_mask()
689 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); in mtk_intx_unmask() local
693 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in mtk_intx_unmask()
694 val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_unmask()
695 val |= BIT(data->hwirq + PCIE_INTX_SHIFT); in mtk_intx_unmask()
696 writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); in mtk_intx_unmask()
697 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in mtk_intx_unmask()
701 * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
705 * until the corresponding de-assert message is received; hence that
710 struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data); in mtk_intx_eoi() local
713 hwirq = data->hwirq + PCIE_INTX_SHIFT; in mtk_intx_eoi()
714 writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG); in mtk_intx_eoi()
727 irq_set_chip_data(irq, domain->host_data); in mtk_pcie_intx_map()
737 static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) in mtk_pcie_init_irq_domains() argument
739 struct device *dev = pcie->dev; in mtk_pcie_init_irq_domains()
740 struct device_node *intc_node, *node = dev->of_node; in mtk_pcie_init_irq_domains()
743 raw_spin_lock_init(&pcie->irq_lock); in mtk_pcie_init_irq_domains()
746 intc_node = of_get_child_by_name(node, "interrupt-controller"); in mtk_pcie_init_irq_domains()
748 dev_err(dev, "missing interrupt-controller node\n"); in mtk_pcie_init_irq_domains()
749 return -ENODEV; in mtk_pcie_init_irq_domains()
752 pcie->intx_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX, in mtk_pcie_init_irq_domains()
753 &intx_domain_ops, pcie); in mtk_pcie_init_irq_domains()
754 if (!pcie->intx_domain) { in mtk_pcie_init_irq_domains()
756 ret = -ENODEV; in mtk_pcie_init_irq_domains()
761 mutex_init(&pcie->lock); in mtk_pcie_init_irq_domains()
766 .host_data = pcie, in mtk_pcie_init_irq_domains()
770 pcie->msi_bottom_domain = msi_create_parent_irq_domain(&info, &mtk_msi_parent_ops); in mtk_pcie_init_irq_domains()
771 if (!pcie->msi_bottom_domain) { in mtk_pcie_init_irq_domains()
773 ret = -ENODEV; in mtk_pcie_init_irq_domains()
781 irq_domain_remove(pcie->intx_domain); in mtk_pcie_init_irq_domains()
787 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) in mtk_pcie_irq_teardown() argument
789 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); in mtk_pcie_irq_teardown()
791 if (pcie->intx_domain) in mtk_pcie_irq_teardown()
792 irq_domain_remove(pcie->intx_domain); in mtk_pcie_irq_teardown()
794 if (pcie->msi_bottom_domain) in mtk_pcie_irq_teardown()
795 irq_domain_remove(pcie->msi_bottom_domain); in mtk_pcie_irq_teardown()
797 irq_dispose_mapping(pcie->irq); in mtk_pcie_irq_teardown()
800 static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx) in mtk_pcie_msi_handler() argument
802 struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx]; in mtk_pcie_msi_handler()
806 msi_enable = readl_relaxed(msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); in mtk_pcie_msi_handler()
809 msi_status = readl_relaxed(msi_set->base + in mtk_pcie_msi_handler()
817 generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq); in mtk_pcie_msi_handler()
824 struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc); in mtk_pcie_irq_handler() local
831 status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG); in mtk_pcie_irq_handler()
834 generic_handle_domain_irq(pcie->intx_domain, in mtk_pcie_irq_handler()
835 irq_bit - PCIE_INTX_SHIFT); in mtk_pcie_irq_handler()
840 mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT); in mtk_pcie_irq_handler()
842 writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG); in mtk_pcie_irq_handler()
848 static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie) in mtk_pcie_setup_irq() argument
850 struct device *dev = pcie->dev; in mtk_pcie_setup_irq()
854 err = mtk_pcie_init_irq_domains(pcie); in mtk_pcie_setup_irq()
858 pcie->irq = platform_get_irq(pdev, 0); in mtk_pcie_setup_irq()
859 if (pcie->irq < 0) in mtk_pcie_setup_irq()
860 return pcie->irq; in mtk_pcie_setup_irq()
862 irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie); in mtk_pcie_setup_irq()
867 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) in mtk_pcie_parse_port() argument
869 int i, ret, num_resets = pcie->soc->phy_resets.num_resets; in mtk_pcie_parse_port()
870 struct device *dev = pcie->dev; in mtk_pcie_parse_port()
875 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); in mtk_pcie_parse_port()
877 return -EINVAL; in mtk_pcie_parse_port()
878 pcie->base = devm_ioremap_resource(dev, regs); in mtk_pcie_parse_port()
879 if (IS_ERR(pcie->base)) { in mtk_pcie_parse_port()
881 return PTR_ERR(pcie->base); in mtk_pcie_parse_port()
884 pcie->reg_base = regs->start; in mtk_pcie_parse_port()
887 pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i]; in mtk_pcie_parse_port()
890 pcie->phy_resets); in mtk_pcie_parse_port()
896 pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac"); in mtk_pcie_parse_port()
897 if (IS_ERR(pcie->mac_reset)) { in mtk_pcie_parse_port()
898 ret = PTR_ERR(pcie->mac_reset); in mtk_pcie_parse_port()
899 if (ret != -EPROBE_DEFER) in mtk_pcie_parse_port()
905 pcie->phy = devm_phy_optional_get(dev, "pcie-phy"); in mtk_pcie_parse_port()
906 if (IS_ERR(pcie->phy)) { in mtk_pcie_parse_port()
907 ret = PTR_ERR(pcie->phy); in mtk_pcie_parse_port()
908 if (ret != -EPROBE_DEFER) in mtk_pcie_parse_port()
914 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); in mtk_pcie_parse_port()
915 if (pcie->num_clks < 0) { in mtk_pcie_parse_port()
917 return pcie->num_clks; in mtk_pcie_parse_port()
920 ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); in mtk_pcie_parse_port()
923 (num_lanes != 1 && num_lanes % 2)) in mtk_pcie_parse_port()
924 dev_warn(dev, "invalid num-lanes, using controller defaults\n"); in mtk_pcie_parse_port()
926 pcie->num_lanes = num_lanes; in mtk_pcie_parse_port()
932 static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) in mtk_pcie_en7581_power_up() argument
934 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_en7581_power_up() local
935 struct device *dev = pcie->dev; in mtk_pcie_en7581_power_up()
946 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, in mtk_pcie_en7581_power_up()
947 pcie->phy_resets); in mtk_pcie_en7581_power_up()
954 * hw to detect if a given address is accessible on PCIe controller. in mtk_pcie_en7581_power_up()
956 pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, in mtk_pcie_en7581_power_up()
957 "mediatek,pbus-csr", in mtk_pcie_en7581_power_up()
963 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); in mtk_pcie_en7581_power_up()
965 return -ENODEV; in mtk_pcie_en7581_power_up()
967 addr = entry->res->start - entry->offset; in mtk_pcie_en7581_power_up()
969 size = lower_32_bits(resource_size(entry->res)); in mtk_pcie_en7581_power_up()
970 regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); in mtk_pcie_en7581_power_up()
974 * requires PHY initialization and power-on before PHY reset deassert. in mtk_pcie_en7581_power_up()
976 err = phy_init(pcie->phy); in mtk_pcie_en7581_power_up()
982 err = phy_power_on(pcie->phy); in mtk_pcie_en7581_power_up()
988 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, in mtk_pcie_en7581_power_up()
989 pcie->phy_resets); in mtk_pcie_en7581_power_up()
996 * Wait for the time needed to complete the bulk de-assert above. in mtk_pcie_en7581_power_up()
1008 writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG); in mtk_pcie_en7581_power_up()
1014 writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); in mtk_pcie_en7581_power_up()
1016 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); in mtk_pcie_en7581_power_up()
1023 * Airoha EN7581 performs PCIe reset via clk callbacks since it has a in mtk_pcie_en7581_power_up()
1025 * complete the PCIe reset. in mtk_pcie_en7581_power_up()
1034 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, in mtk_pcie_en7581_power_up()
1035 pcie->phy_resets); in mtk_pcie_en7581_power_up()
1037 phy_power_off(pcie->phy); in mtk_pcie_en7581_power_up()
1039 phy_exit(pcie->phy); in mtk_pcie_en7581_power_up()
1044 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) in mtk_pcie_power_up() argument
1046 struct device *dev = pcie->dev; in mtk_pcie_power_up()
1053 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, in mtk_pcie_power_up()
1054 pcie->phy_resets); in mtk_pcie_power_up()
1055 reset_control_assert(pcie->mac_reset); in mtk_pcie_power_up()
1059 err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, in mtk_pcie_power_up()
1060 pcie->phy_resets); in mtk_pcie_power_up()
1066 err = phy_init(pcie->phy); in mtk_pcie_power_up()
1072 err = phy_power_on(pcie->phy); in mtk_pcie_power_up()
1079 reset_control_deassert(pcie->mac_reset); in mtk_pcie_power_up()
1084 err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); in mtk_pcie_power_up()
1095 reset_control_assert(pcie->mac_reset); in mtk_pcie_power_up()
1096 phy_power_off(pcie->phy); in mtk_pcie_power_up()
1098 phy_exit(pcie->phy); in mtk_pcie_power_up()
1100 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, in mtk_pcie_power_up()
1101 pcie->phy_resets); in mtk_pcie_power_up()
1106 static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie) in mtk_pcie_power_down() argument
1108 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); in mtk_pcie_power_down()
1110 pm_runtime_put_sync(pcie->dev); in mtk_pcie_power_down()
1111 pm_runtime_disable(pcie->dev); in mtk_pcie_power_down()
1112 reset_control_assert(pcie->mac_reset); in mtk_pcie_power_down()
1114 phy_power_off(pcie->phy); in mtk_pcie_power_down()
1115 phy_exit(pcie->phy); in mtk_pcie_power_down()
1116 reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, in mtk_pcie_power_down()
1117 pcie->phy_resets); in mtk_pcie_power_down()
1120 static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie) in mtk_pcie_get_controller_max_link_speed() argument
1125 val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG); in mtk_pcie_get_controller_max_link_speed()
1129 return ret > 0 ? ret : -EINVAL; in mtk_pcie_get_controller_max_link_speed()
1132 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) in mtk_pcie_setup() argument
1136 err = mtk_pcie_parse_port(pcie); in mtk_pcie_setup()
1144 reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, in mtk_pcie_setup()
1145 pcie->phy_resets); in mtk_pcie_setup()
1148 err = pcie->soc->power_up(pcie); in mtk_pcie_setup()
1152 err = of_pci_get_max_link_speed(pcie->dev->of_node); in mtk_pcie_setup()
1155 max_speed = mtk_pcie_get_controller_max_link_speed(pcie); in mtk_pcie_setup()
1159 pcie->max_link_speed = err; in mtk_pcie_setup()
1160 dev_info(pcie->dev, in mtk_pcie_setup()
1162 max_speed, pcie->max_link_speed); in mtk_pcie_setup()
1167 err = mtk_pcie_startup_port(pcie); in mtk_pcie_setup()
1171 err = mtk_pcie_setup_irq(pcie); in mtk_pcie_setup()
1178 mtk_pcie_power_down(pcie); in mtk_pcie_setup()
1185 struct device *dev = &pdev->dev; in mtk_pcie_probe()
1186 struct mtk_gen3_pcie *pcie; in mtk_pcie_probe() local
1187 struct pci_host_bridge *host; in mtk_pcie_probe() local
1190 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in mtk_pcie_probe()
1191 if (!host) in mtk_pcie_probe()
1192 return -ENOMEM; in mtk_pcie_probe()
1194 pcie = pci_host_bridge_priv(host); in mtk_pcie_probe()
1196 pcie->dev = dev; in mtk_pcie_probe()
1197 pcie->soc = device_get_match_data(dev); in mtk_pcie_probe()
1198 platform_set_drvdata(pdev, pcie); in mtk_pcie_probe()
1200 err = mtk_pcie_setup(pcie); in mtk_pcie_probe()
1204 host->ops = &mtk_pcie_ops; in mtk_pcie_probe()
1205 host->sysdata = pcie; in mtk_pcie_probe()
1207 err = pci_host_probe(host); in mtk_pcie_probe()
1209 mtk_pcie_irq_teardown(pcie); in mtk_pcie_probe()
1210 mtk_pcie_power_down(pcie); in mtk_pcie_probe()
1219 struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev); in mtk_pcie_remove() local
1220 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); in mtk_pcie_remove() local
1223 pci_stop_root_bus(host->bus); in mtk_pcie_remove()
1224 pci_remove_root_bus(host->bus); in mtk_pcie_remove()
1227 mtk_pcie_irq_teardown(pcie); in mtk_pcie_remove()
1228 mtk_pcie_power_down(pcie); in mtk_pcie_remove()
1231 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) in mtk_pcie_irq_save() argument
1235 raw_spin_lock(&pcie->irq_lock); in mtk_pcie_irq_save()
1237 pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_irq_save()
1240 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_irq_save()
1242 msi_set->saved_irq_state = readl_relaxed(msi_set->base + in mtk_pcie_irq_save()
1246 raw_spin_unlock(&pcie->irq_lock); in mtk_pcie_irq_save()
1249 static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie) in mtk_pcie_irq_restore() argument
1253 raw_spin_lock(&pcie->irq_lock); in mtk_pcie_irq_restore()
1255 writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG); in mtk_pcie_irq_restore()
1258 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_irq_restore()
1260 writel_relaxed(msi_set->saved_irq_state, in mtk_pcie_irq_restore()
1261 msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); in mtk_pcie_irq_restore()
1264 raw_spin_unlock(&pcie->irq_lock); in mtk_pcie_irq_restore()
1267 static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie) in mtk_pcie_turn_off_link() argument
1271 val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG); in mtk_pcie_turn_off_link()
1273 writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG); in mtk_pcie_turn_off_link()
1276 return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val, in mtk_pcie_turn_off_link()
1284 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); in mtk_pcie_suspend_noirq() local
1289 err = mtk_pcie_turn_off_link(pcie); in mtk_pcie_suspend_noirq()
1291 dev_err(pcie->dev, "cannot enter L2 state\n"); in mtk_pcie_suspend_noirq()
1295 if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { in mtk_pcie_suspend_noirq()
1297 val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_suspend_noirq()
1299 writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); in mtk_pcie_suspend_noirq()
1302 dev_dbg(pcie->dev, "entered L2 states successfully"); in mtk_pcie_suspend_noirq()
1304 mtk_pcie_irq_save(pcie); in mtk_pcie_suspend_noirq()
1305 mtk_pcie_power_down(pcie); in mtk_pcie_suspend_noirq()
1312 struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev); in mtk_pcie_resume_noirq() local
1315 err = pcie->soc->power_up(pcie); in mtk_pcie_resume_noirq()
1319 err = mtk_pcie_startup_port(pcie); in mtk_pcie_resume_noirq()
1321 mtk_pcie_power_down(pcie); in mtk_pcie_resume_noirq()
1325 mtk_pcie_irq_restore(pcie); in mtk_pcie_resume_noirq()
1339 .num_resets = 1,
1347 .num_resets = 1,
1355 .id[0] = "phy-lane0",
1356 .id[1] = "phy-lane1",
1357 .id[2] = "phy-lane2",
1364 { .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
1365 { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
1366 { .compatible = "mediatek,mt8196-pcie", .data = &mtk_pcie_soc_mt8196 },
1375 .name = "mtk-pcie-gen3",
1383 MODULE_DESCRIPTION("MediaTek Gen3 PCIe host controller driver");