Lines Matching +full:msi +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/msi.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
175 /* MSI target addresses */
189 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
190 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
201 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
202 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
203 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
204 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG])
205 #define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE])
245 * The RESCAL block is tied to PCIe controller #1, regardless of the number of
246 * controllers, and turning off PCIe controller #1 prevents access to the RESCAL
281 int nr; /* No. of MSI available, depends on chip */
295 struct brcm_msi *msi; member
310 return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425; in is_bmips()
315 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
323 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
326 return log2_in - 15; in brcm_pcie_encode_ibar_size()
386 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
391 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
396 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); in brcm_pcie_set_ssc()
397 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); in brcm_pcie_set_ssc()
398 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
404 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
412 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
415 /* Limits operation to a specific generation (1, 2, or 3) */
418 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
419 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
422 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
425 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
438 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
439 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
443 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
445 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
450 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
460 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
463 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
466 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
469 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
484 .prefix = "BRCM-",
492 struct brcm_msi *msi; in brcm_pcie_msi_isr() local
497 msi = irq_desc_get_handler_data(desc); in brcm_pcie_msi_isr()
498 dev = msi->dev; in brcm_pcie_msi_isr()
500 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
501 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
503 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
505 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
507 dev_dbg(dev, "unexpected MSI\n"); in brcm_pcie_msi_isr()
515 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); in brcm_msi_compose_msi_msg() local
517 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
518 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
519 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
524 struct brcm_msi *msi = irq_data_get_irq_chip_data(data); in brcm_msi_ack_irq() local
525 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
527 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
532 .name = "BRCM STB MSI",
537 static int brcm_msi_alloc(struct brcm_msi *msi, unsigned int nr_irqs) in brcm_msi_alloc() argument
541 mutex_lock(&msi->lock); in brcm_msi_alloc()
542 hwirq = bitmap_find_free_region(msi->used, msi->nr, in brcm_msi_alloc()
544 mutex_unlock(&msi->lock); in brcm_msi_alloc()
549 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq, in brcm_msi_free() argument
552 mutex_lock(&msi->lock); in brcm_msi_free()
553 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); in brcm_msi_free()
554 mutex_unlock(&msi->lock); in brcm_msi_free()
560 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc() local
563 hwirq = brcm_msi_alloc(msi, nr_irqs); in brcm_irq_domain_alloc()
570 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
579 struct brcm_msi *msi = irq_data_get_irq_chip_data(d); in brcm_irq_domain_free() local
581 brcm_msi_free(msi, d->hwirq, nr_irqs); in brcm_irq_domain_free()
589 static int brcm_allocate_domains(struct brcm_msi *msi) in brcm_allocate_domains() argument
591 struct device *dev = msi->dev; in brcm_allocate_domains()
594 .fwnode = of_fwnode_handle(msi->np), in brcm_allocate_domains()
596 .host_data = msi, in brcm_allocate_domains()
597 .size = msi->nr, in brcm_allocate_domains()
600 msi->inner_domain = msi_create_parent_irq_domain(&info, &brcm_msi_parent_ops); in brcm_allocate_domains()
601 if (!msi->inner_domain) { in brcm_allocate_domains()
602 dev_err(dev, "failed to create MSI domain\n"); in brcm_allocate_domains()
603 return -ENOMEM; in brcm_allocate_domains()
609 static void brcm_free_domains(struct brcm_msi *msi) in brcm_free_domains() argument
611 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
616 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove() local
618 if (!msi) in brcm_msi_remove()
620 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
621 brcm_free_domains(msi); in brcm_msi_remove()
624 static void brcm_msi_set_regs(struct brcm_msi *msi) in brcm_msi_set_regs() argument
626 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
629 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
630 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
633 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
634 * enable, which we set to 1. in brcm_msi_set_regs()
636 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
637 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
638 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
639 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
641 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
642 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
647 struct brcm_msi *msi; in brcm_pcie_enable_msi() local
649 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
651 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
653 dev_err(dev, "cannot map MSI interrupt\n"); in brcm_pcie_enable_msi()
654 return -ENODEV; in brcm_pcie_enable_msi()
657 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL); in brcm_pcie_enable_msi()
658 if (!msi) in brcm_pcie_enable_msi()
659 return -ENOMEM; in brcm_pcie_enable_msi()
661 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
662 msi->dev = dev; in brcm_pcie_enable_msi()
663 msi->base = pcie->base; in brcm_pcie_enable_msi()
664 msi->np = pcie->np; in brcm_pcie_enable_msi()
665 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
666 msi->irq = irq; in brcm_pcie_enable_msi()
667 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
675 if (msi->legacy) { in brcm_pcie_enable_msi()
676 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); in brcm_pcie_enable_msi()
677 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
678 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
680 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
681 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
682 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
685 ret = brcm_allocate_domains(msi); in brcm_pcie_enable_msi()
689 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
691 brcm_msi_set_regs(msi); in brcm_pcie_enable_msi()
692 pcie->msi = msi; in brcm_pcie_enable_msi()
700 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
708 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
718 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus()
719 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
726 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
731 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
739 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus()
740 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
747 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
752 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
763 if (pcie->bridge_reset) { in brcm_pcie_bridge_sw_init_set_generic()
765 ret = reset_control_assert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
767 ret = reset_control_deassert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
770 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", in brcm_pcie_bridge_sw_init_set_generic()
776 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
778 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
788 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
790 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
799 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
800 return -EINVAL; in brcm_pcie_perst_set_4908()
803 ret = reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
805 ret = reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
808 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", in brcm_pcie_perst_set_4908()
818 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
820 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
829 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
831 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
845 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); in brcm_pcie_post_setup_bcm2712()
850 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); in brcm_pcie_post_setup_bcm2712()
858 * Set L1SS sub-state timers to avoid lengthy state transitions, in brcm_pcie_post_setup_bcm2712()
859 * PM clock period is 18.52ns (1/54MHz, round down). in brcm_pcie_post_setup_bcm2712()
861 tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); in brcm_pcie_post_setup_bcm2712()
864 writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); in brcm_pcie_post_setup_bcm2712()
872 b->size = size; in add_inbound_win()
873 b->cpu_addr = cpu_addr; in add_inbound_win()
874 b->pci_offset = pci_offset; in add_inbound_win()
884 struct device *dev = pcie->dev; in brcm_pcie_get_inbound_wins()
890 * The HW registers (and PCIe) use order-1 numbering for BARs. As such, in brcm_pcie_get_inbound_wins()
891 * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. in brcm_pcie_get_inbound_wins()
893 struct inbound_win *b_begin = &inbound_wins[1]; in brcm_pcie_get_inbound_wins()
903 if (pcie->cfg->soc_base != BCM7712) in brcm_pcie_get_inbound_wins()
906 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_inbound_wins()
907 u64 pcie_start = entry->res->start - entry->offset; in brcm_pcie_get_inbound_wins()
908 u64 cpu_start = entry->res->start; in brcm_pcie_get_inbound_wins()
910 size = resource_size(entry->res); in brcm_pcie_get_inbound_wins()
916 * offering a non-overlapping viewport to system memory. in brcm_pcie_get_inbound_wins()
920 if (pcie->cfg->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
923 if (n > pcie->cfg->num_inbound_wins) in brcm_pcie_get_inbound_wins()
928 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_inbound_wins()
929 return -EINVAL; in brcm_pcie_get_inbound_wins()
937 if (pcie->cfg->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
940 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_inbound_wins()
944 pcie->num_memc = 1; in brcm_pcie_get_inbound_wins()
945 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
947 pcie->num_memc = ret; in brcm_pcie_get_inbound_wins()
951 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
952 size += pcie->memc_size[i]; in brcm_pcie_get_inbound_wins()
955 size = 1ULL << fls64(size - 1); in brcm_pcie_get_inbound_wins()
966 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_inbound_wins()
968 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_inbound_wins()
970 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_inbound_wins()
971 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_inbound_wins()
977 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_inbound_wins()
979 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_inbound_wins()
980 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_inbound_wins()
987 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_inbound_wins()
988 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_inbound_wins()
989 * only address 32bits. We would also like to put the MSI under 4GB in brcm_pcie_get_inbound_wins()
990 * as well, since some devices require a 32bit MSI target address. in brcm_pcie_get_inbound_wins()
992 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_inbound_wins()
994 * outbound memory @ 3GB). So instead it will start at the 1x in brcm_pcie_get_inbound_wins()
997 if (!size || (pci_offset & (size - 1)) || in brcm_pcie_get_inbound_wins()
1001 return -EINVAL; in brcm_pcie_get_inbound_wins()
1019 return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); in brcm_bar_reg_offset()
1021 return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); in brcm_bar_reg_offset()
1027 return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); in brcm_ubus_reg_offset()
1029 return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); in brcm_ubus_reg_offset()
1036 void __iomem *base = pcie->base; in set_inbound_win_registers()
1039 for (i = 1; i <= num_inbound_wins; i++) { in set_inbound_win_registers()
1060 if (pcie->cfg->soc_base == BCM7712) { in set_inbound_win_registers()
1075 void __iomem *base = pcie->base; in brcm_pcie_setup()
1084 ret = pcie->cfg->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
1089 if (pcie->cfg->soc_base == BCM2711) { in brcm_pcie_setup()
1090 ret = pcie->cfg->perst_set(pcie, 1); in brcm_pcie_setup()
1092 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1100 ret = pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1115 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
1116 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
1120 else if (pcie->cfg->soc_base == BCM2711) in brcm_pcie_setup()
1122 else if (pcie->cfg->soc_base == BCM7278) in brcm_pcie_setup()
1132 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); in brcm_pcie_setup()
1133 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); in brcm_pcie_setup()
1135 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK); in brcm_pcie_setup()
1136 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); in brcm_pcie_setup()
1146 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
1147 return -EINVAL; in brcm_pcie_setup()
1151 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1152 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
1156 else if (memc == 1) in brcm_pcie_setup()
1157 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1)); in brcm_pcie_setup()
1164 * We ideally want the MSI target address to be located in the 32bit in brcm_pcie_setup()
1168 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
1172 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
1174 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
1177 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
1179 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1192 * "num-lanes" DT property is present, assume that the chip's default in brcm_pcie_setup()
1196 if (!of_property_read_u32(pcie->np, "num-lanes", &num_lanes) && in brcm_pcie_setup()
1202 u32p_replace_bits(&tmp, 1, in brcm_pcie_setup()
1209 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1217 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
1218 struct resource *res = entry->res; in brcm_pcie_setup()
1224 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1225 return -EINVAL; in brcm_pcie_setup()
1229 u64 start = res->start; in brcm_pcie_setup()
1237 start - entry->offset, in brcm_pcie_setup()
1241 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1242 res->start - entry->offset, in brcm_pcie_setup()
1247 /* PCIe->SCB endian mode for inbound window */ in brcm_pcie_setup()
1253 if (pcie->cfg->post_setup) { in brcm_pcie_setup()
1254 ret = pcie->cfg->post_setup(pcie); in brcm_pcie_setup()
1270 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1274 if (pcie->cfg->soc_base == BCM7712) in brcm_extend_rbus_timeout()
1277 /* Each unit in timeout register is 1/216,000,000 seconds */ in brcm_extend_rbus_timeout()
1278 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1283 static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; in brcm_config_clkreq()
1288 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1289 if (ret && ret != -EINVAL) { in brcm_config_clkreq()
1290 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1295 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1298 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1300 * "no-l1ss" -- Provides Clock Power Management, L0s, and in brcm_config_clkreq()
1308 * We want to un-advertise L1 substates because if the OS in brcm_config_clkreq()
1311 * "no-l1ss" mode. in brcm_config_clkreq()
1313 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1315 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1319 * "default" -- Provides L0s, L1, and L1SS, but not in brcm_config_clkreq()
1331 * "safe" -- No power savings; refclk is driven by RC in brcm_config_clkreq()
1335 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1338 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1340 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1345 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1346 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1352 if (pcie->gen) in brcm_pcie_start_link()
1353 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1356 ret = pcie->cfg->perst_set(pcie, 0); in brcm_pcie_start_link()
1364 * configure RC. Intermittently check status for link-up, up to a in brcm_pcie_start_link()
1372 return -ENODEV; in brcm_pcie_start_link()
1377 if (pcie->ssc) { in brcm_pcie_start_link()
1410 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1412 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1420 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus()
1421 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1425 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1428 if (dev->of_node) { in brcm_pcie_add_bus()
1435 pcie->sr = sr; in brcm_pcie_add_bus()
1437 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1440 pcie->sr = NULL; in brcm_pcie_add_bus()
1444 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1447 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1448 pcie->sr = NULL; in brcm_pcie_add_bus()
1459 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus()
1460 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1461 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1463 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_remove_bus()
1466 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1468 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1469 pcie->sr = NULL; in brcm_pcie_remove_bus()
1472 /* L23 is a low-power PCIe link state */
1475 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1481 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_enter_l23()
1495 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1508 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1509 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1512 void __iomem *base = pcie->base; in brcm_phy_cntl()
1515 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1527 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1529 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1536 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1541 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1546 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1552 ret = pcie->cfg->perst_set(pcie, 1); in brcm_pcie_turn_off()
1563 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_turn_off()
1566 if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) in brcm_pcie_turn_off()
1568 ret = pcie->cfg->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1577 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1579 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1602 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1608 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1611 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1614 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1615 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1616 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1617 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1618 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1619 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1622 rret = reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1630 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1642 base = pcie->base; in brcm_pcie_resume_noirq()
1643 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1647 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1656 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1670 if (pcie->sr) { in brcm_pcie_resume_noirq()
1671 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1678 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1680 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1681 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1693 if (pcie->msi) in brcm_pcie_resume_noirq()
1694 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1699 if (pcie->sr) in brcm_pcie_resume_noirq()
1700 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1702 rret = reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1704 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); in brcm_pcie_resume_noirq()
1706 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1715 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1716 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1717 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1718 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1726 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1727 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1839 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1840 { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
1841 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1842 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1843 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1844 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1845 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1846 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1847 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1848 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1870 struct device_node *np = pdev->dev.of_node; in brcm_pcie_probe()
1876 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1878 return -ENOMEM; in brcm_pcie_probe()
1880 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1883 return -EINVAL; in brcm_pcie_probe()
1887 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1888 pcie->np = np; in brcm_pcie_probe()
1889 pcie->cfg = data; in brcm_pcie_probe()
1891 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1892 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1893 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1895 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1896 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1897 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1900 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1902 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1904 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1905 if (IS_ERR(pcie->rescal)) in brcm_pcie_probe()
1906 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1908 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1909 if (IS_ERR(pcie->perst_reset)) in brcm_pcie_probe()
1910 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1912 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); in brcm_pcie_probe()
1913 if (IS_ERR(pcie->bridge_reset)) in brcm_pcie_probe()
1914 return PTR_ERR(pcie->bridge_reset); in brcm_pcie_probe()
1916 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); in brcm_pcie_probe()
1917 if (IS_ERR(pcie->swinit_reset)) in brcm_pcie_probe()
1918 return PTR_ERR(pcie->swinit_reset); in brcm_pcie_probe()
1920 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1922 return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); in brcm_pcie_probe()
1924 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1926 if (pcie->swinit_reset) { in brcm_pcie_probe()
1927 ret = reset_control_assert(pcie->swinit_reset); in brcm_pcie_probe()
1929 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1930 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1934 /* HW team recommends 1us for proper sync and propagation of reset */ in brcm_pcie_probe()
1935 udelay(1); in brcm_pcie_probe()
1937 ret = reset_control_deassert(pcie->swinit_reset); in brcm_pcie_probe()
1939 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1940 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1941 "could not de-assert reset 'swinit'\n"); in brcm_pcie_probe()
1945 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1947 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1948 return dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1953 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1954 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1962 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1963 if (pcie->cfg->soc_base == BCM4908 && in brcm_pcie_probe()
1964 pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1965 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1966 ret = -ENODEV; in brcm_pcie_probe()
1971 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1973 if (msi_np == pcie->np) in brcm_pcie_probe()
1979 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1984 bridge->ops = pcie->cfg->soc_base == BCM7425 ? in brcm_pcie_probe()
1986 bridge->sysdata = pcie; in brcm_pcie_probe()
1992 ret = -ENODEV; in brcm_pcie_probe()
2018 .name = "brcm-pcie",