Lines Matching +full:0 +full:x4048
39 #define BRCM_PCIE_CAP_REGS 0x00ac
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
43 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
44 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
46 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
47 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
50 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_MAX_LINK_WIDTH_MASK 0x1f0
51 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
53 #define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8
54 #define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8
56 #define PCIE_RC_DL_MDIO_ADDR 0x1100
57 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
58 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
60 #define PCIE_RC_PL_REG_PHY_CTL_1 0x1804
61 #define PCIE_RC_PL_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_MASK 0x8
63 #define PCIE_RC_PL_PHY_CTL_15 0x184c
64 #define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000
65 #define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff
67 #define PCIE_MISC_MISC_CTRL 0x4008
68 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
69 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
70 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
71 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
72 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
74 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
75 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
76 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
79 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
83 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
95 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
96 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
98 #define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
101 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
102 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
104 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
105 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
106 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
108 #define PCIE_MISC_PCIE_CTRL 0x4064
109 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
110 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
112 #define PCIE_MISC_PCIE_STATUS 0x4068
113 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
114 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
115 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
116 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
118 #define PCIE_MISC_REVISION 0x406c
119 #define BRCM_PCIE_HW_REV_33 0x0303
120 #define BRCM_PCIE_HW_REV_3_20 0x0320
122 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
123 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
124 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
128 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
129 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
133 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
134 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
138 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
139 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
140 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
141 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
146 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
147 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0)
148 #define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c
150 #define PCIE_MSI_INTR2_BASE 0x4500
153 #define MSI_INT_STATUS 0x0
154 #define MSI_INT_CLR 0x8
155 #define MSI_INT_MASK_SET 0x10
156 #define MSI_INT_MASK_CLR 0x14
158 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
159 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
161 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
162 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
163 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
164 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
167 #define BRCM_NUM_PCIE_OUT_WINS 0x4
170 #define BRCM_INT_PCI_MSI_SHIFT 0
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
176 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
177 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
180 #define MDIO_PORT0 0x0
181 #define MDIO_DATA_MASK 0x7fffffff
182 #define MDIO_PORT_MASK 0xf0000
183 #define MDIO_PORT_EXT_MASK 0x200000
184 #define MDIO_REGAD_MASK 0xffff
185 #define MDIO_CMD_MASK 0x00100000
186 #define MDIO_CMD_READ 0x1
187 #define MDIO_CMD_WRITE 0x0
188 #define MDIO_DATA_DONE_MASK 0x80000000
189 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
190 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
191 #define SSC_REGS_ADDR 0x1100
192 #define SET_ADDR_OFFSET 0x1f
193 #define SSC_CNTL_OFFSET 0x2
194 #define SSC_CNTL_OVRD_EN_MASK 0x8000
195 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
196 #define SSC_STATUS_OFFSET 0x1
197 #define SSC_STATUS_SSC_MASK 0x400
198 #define SSC_STATUS_PLL_LOCK_MASK 0x800
208 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
209 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
210 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
211 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
212 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
213 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
214 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
215 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
251 #define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0)
323 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
328 return 0; in brcm_pcie_encode_ibar_size()
333 u32 pkt = 0; in brcm_pcie_mdio_form_pkt()
388 if (ret < 0) in brcm_pcie_set_ssc()
393 if (ret < 0) in brcm_pcie_set_ssc()
400 if (ret < 0) in brcm_pcie_set_ssc()
406 if (ret < 0) in brcm_pcie_set_ssc()
412 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
519 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
565 if (hwirq < 0) in brcm_irq_domain_alloc()
568 for (i = 0; i < nr_irqs; i++) in brcm_irq_domain_alloc()
572 return 0; in brcm_irq_domain_alloc()
606 return 0; in brcm_allocate_domains()
633 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
636 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
652 if (irq <= 0) { in brcm_pcie_enable_msi()
682 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
694 return 0; in brcm_pcie_enable_msi()
731 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
761 int ret = 0; in brcm_pcie_bridge_sw_init_set_generic()
792 return 0; in brcm_pcie_bridge_sw_init_set_7278()
817 /* Perst bit has moved and assert value is 0 */ in brcm_pcie_perst_set_7278()
822 return 0; in brcm_pcie_perst_set_7278()
833 return 0; in brcm_pcie_perst_set_generic()
838 static const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, in brcm_pcie_post_setup_bcm2712()
839 0x5030, 0x0007 }; in brcm_pcie_post_setup_bcm2712()
840 static const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; in brcm_pcie_post_setup_bcm2712()
845 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); in brcm_pcie_post_setup_bcm2712()
846 if (ret < 0) in brcm_pcie_post_setup_bcm2712()
849 for (i = 0; i < ARRAY_SIZE(regs); i++) { in brcm_pcie_post_setup_bcm2712()
851 if (ret < 0) in brcm_pcie_post_setup_bcm2712()
863 tmp |= 0x12; in brcm_pcie_post_setup_bcm2712()
866 return 0; in brcm_pcie_post_setup_bcm2712()
882 u64 pci_offset, cpu_addr, size = 0, tot_size = 0; in brcm_pcie_get_inbound_wins()
885 u64 lowest_pcie_addr = ~(u64)0; in brcm_pcie_get_inbound_wins()
886 int ret, i = 0; in brcm_pcie_get_inbound_wins()
887 u8 n = 0; in brcm_pcie_get_inbound_wins()
891 * we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. in brcm_pcie_get_inbound_wins()
904 add_inbound_win(b++, &n, 0, 0, 0); in brcm_pcie_get_inbound_wins()
927 if (lowest_pcie_addr == ~(u64)0) { in brcm_pcie_get_inbound_wins()
942 if (ret <= 0) { in brcm_pcie_get_inbound_wins()
945 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
951 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
959 * of system memory, so we set it to 0. in brcm_pcie_get_inbound_wins()
961 cpu_addr = 0; in brcm_pcie_get_inbound_wins()
993 * region at location 0 (since we have to allow some space for in brcm_pcie_get_inbound_wins()
999 dev_err(dev, "Invalid inbound_win2_offset/size: size 0x%llx, off 0x%llx\n", in brcm_pcie_get_inbound_wins()
1011 add_inbound_win(b++, &n, 0, 0, 0); in brcm_pcie_get_inbound_wins()
1063 tmp = lower_32_bits(cpu_addr) & ~0xfff; in set_inbound_win_registers()
1079 u8 num_out_wins = 0; in brcm_pcie_setup()
1080 int num_inbound_wins = 0; in brcm_pcie_setup()
1092 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1100 ret = pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1115 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
1116 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
1119 burst = 0x1; /* 256 bytes */ in brcm_pcie_setup()
1121 burst = 0x0; /* 128 bytes */ in brcm_pcie_setup()
1123 burst = 0x3; /* 512 bytes */ in brcm_pcie_setup()
1125 burst = 0x2; /* 512 bytes */ in brcm_pcie_setup()
1140 if (num_inbound_wins < 0) in brcm_pcie_setup()
1151 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1154 if (memc == 0) in brcm_pcie_setup()
1155 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); in brcm_pcie_setup()
1188 num_lanes = 0; in brcm_pcie_setup()
1212 u32p_replace_bits(&tmp, 0x060400, in brcm_pcie_setup()
1235 for (j = 0; j < nwins; j++, start += SZ_128M) in brcm_pcie_setup()
1255 if (ret < 0) in brcm_pcie_setup()
1259 return 0; in brcm_pcie_setup()
1298 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1317 } else if (strcmp(mode, "default") == 0) { in brcm_config_clkreq()
1334 if (strcmp(mode, "safe") != 0) in brcm_config_clkreq()
1356 ret = pcie->cfg->perst_set(pcie, 0); in brcm_pcie_start_link()
1367 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1379 if (ret == 0) in brcm_pcie_start_link()
1392 return 0; in brcm_pcie_start_link()
1411 for (i = 0; i < ARRAY_SIZE(supplies); i++) in alloc_subdev_regulators()
1426 return 0; in brcm_pcie_add_bus()
1454 return 0; in brcm_pcie_add_bus()
1487 for (i = 0; i < 15 && !l23; i++) { in brcm_pcie_enter_l23()
1508 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1510 u32 tmp, combined_mask = 0; in brcm_phy_cntl()
1516 val = start ? BIT_MASK(shifts[i]) : 0; in brcm_phy_cntl()
1525 val = start ? combined_mask : 0; in brcm_phy_cntl()
1527 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1536 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1541 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1558 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_turn_off()
1632 return 0; in brcm_pcie_suspend_noirq()
1656 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1658 /* SERDES_IDDQ = 0 */ in brcm_pcie_resume_noirq()
1660 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_resume_noirq()
1696 return 0; in brcm_pcie_resume_noirq()
1732 [RGR1_SW_INIT_1] = 0x9210,
1733 [EXT_CFG_INDEX] = 0x9000,
1734 [EXT_CFG_DATA] = 0x8000,
1735 [PCIE_HARD_DEBUG] = 0x4204,
1736 [PCIE_INTR2_CPU_BASE] = 0x4300,
1740 [RGR1_SW_INIT_1] = 0xc010,
1741 [EXT_CFG_INDEX] = 0x9000,
1742 [EXT_CFG_DATA] = 0x8000,
1743 [PCIE_HARD_DEBUG] = 0x4204,
1744 [PCIE_INTR2_CPU_BASE] = 0x4300,
1748 [RGR1_SW_INIT_1] = 0x8010,
1749 [EXT_CFG_INDEX] = 0x8300,
1750 [EXT_CFG_DATA] = 0x8304,
1751 [PCIE_HARD_DEBUG] = 0x4204,
1752 [PCIE_INTR2_CPU_BASE] = 0x4300,
1756 [RGR1_SW_INIT_1] = 0x9210,
1757 [EXT_CFG_INDEX] = 0x9000,
1758 [EXT_CFG_DATA] = 0x8000,
1759 [PCIE_HARD_DEBUG] = 0x4304,
1760 [PCIE_INTR2_CPU_BASE] = 0x4400,
1891 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1900 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1924 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1971 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1999 return 0; in brcm_pcie_probe()