24 #define RP_TX_REG0			0x2000
25 #define RP_TX_REG1			0x2004
26 #define RP_TX_CNTRL			0x2008
27 #define RP_TX_EOP			0x2
28 #define RP_TX_SOP			0x1
29 #define RP_RXCPL_STATUS			0x2010
30 #define RP_RXCPL_EOP			0x2
31 #define RP_RXCPL_SOP			0x1
32 #define RP_RXCPL_REG0			0x2014
33 #define RP_RXCPL_REG1			0x2018
34 #define P2A_INT_STATUS			0x3060
35 #define P2A_INT_STS_ALL			0xf
36 #define P2A_INT_ENABLE			0x3070
37 #define P2A_INT_ENA_ALL			0xf
38 #define RP_LTSSM			0x3c64
39 #define RP_LTSSM_MASK			0x1f
40 #define LTSSM_L0			0xf
42 #define S10_RP_TX_CNTRL			0x2004
43 #define S10_RP_RXCPL_REG		0x2008
44 #define S10_RP_RXCPL_STATUS		0x200C
50 /* TLP configuration type 0 and 1 */
51 #define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */
52 #define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
53 #define TLP_FMTTYPE_CFGRD1		0x05	/* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1		0x45	/* Configuration Write Type 1 */
55 #define TLP_PAYLOAD_SIZE		0x01
56 #define TLP_READ_TAG			0x1d
57 #define TLP_WRITE_TAG			0x10
58 #define RP_DEVFN			0
67 #define TLP_BYTE_COUNT(s)		(((s) >> 0) & 0xfff)
76 #define S10_TLP_FMTTYPE_CFGRD0		0x05
77 #define S10_TLP_FMTTYPE_CFGRD1		0x04
78 #define S10_TLP_FMTTYPE_CFGWR0		0x45
79 #define S10_TLP_FMTTYPE_CFGWR1		0x44
85 #define AGLX_BDF_REG			0x00002004
86 #define AGLX_ROOT_PORT_IRQ_STATUS	0x14c
87 #define AGLX_ROOT_PORT_IRQ_ENABLE	0x150
91 #define AGLX_CFG_TARGET_TYPE0		0
97 	ALTERA_PCIE_V1 = 0,
216 	if (pci_is_root_bus(bus) && (devfn == 0) &&  in altera_pcie_hide_rc_bar()
247 	if (bus->number == pcie->root_bus_nr && dev > 0)  in altera_pcie_valid_device()
265 	for (i = 0; i < TLP_LOOP; i++) {  in tlp_read_packet()
300 	for (count = 0; count < TLP_LOOP; count++) {  in s10_tlp_read_packet()
304 			dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);  in s10_tlp_read_packet()
344 	tlp_rp_regdata.reg0 = headers[0];  in tlp_write_packet()
351 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
352 		tlp_rp_regdata.ctrl = 0;  in tlp_write_packet()
356 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
369 	s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);  in s10_tlp_write_packet()
370 	s10_tlp_write_tx(pcie, headers[1], 0);  in s10_tlp_write_packet()
371 	s10_tlp_write_tx(pcie, headers[2], 0);  in s10_tlp_write_packet()
388 	headers[0] = TLP_CFG_DW0(pcie, cfg);  in get_tlp_header()
401 	pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);  in tlp_cfg_dword_read()
416 	if ((where & 0x7) == 0)  in tlp_cfg_dword_write()
479 		pcie->root_bus_nr = value & 0xff;  in s10_rp_write_cfg()
503 		*value = 0x01;  in aglx_rp_read_cfg()
504 	else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00))  in aglx_rp_read_cfg()
505 		*value |= 0x0100;  in aglx_rp_read_cfg()
532 		pcie->root_bus_nr = value & 0xff;  in aglx_rp_write_cfg()
605 		byte_en = 0xf;  in _altera_pcie_cfg_read()
616 		*value = (data >> (8 * (where & 0x3))) & 0xff;  in _altera_pcie_cfg_read()
619 		*value = (data >> (8 * (where & 0x2))) & 0xffff;  in _altera_pcie_cfg_read()
647 		data32 = (value & 0xff) << shift;  in _altera_pcie_cfg_write()
651 		data32 = (value & 0xffff) << shift;  in _altera_pcie_cfg_write()
656 		byte_en = 0xf;  in _altera_pcie_cfg_write()
791 	return 0;  in altera_pcie_intx_map()
813 		& P2A_INT_STS_ALL) != 0) {  in altera_pcie_isr()
845 		ret = generic_handle_domain_irq(pcie->irq_domain, 0);  in aglx_isr()
865 	return 0;  in altera_pcie_init_irq_domain()
891 	pcie->irq = platform_get_irq(pdev, 0);  in altera_pcie_parse_dt()
892 	if (pcie->irq < 0)  in altera_pcie_parse_dt()
896 	return 0;  in altera_pcie_parse_dt()
931 	.cap_offset = 0x80,
942 	.cap_offset = 0x70,
952 	.cap_offset = 0x70,
953 	.port_conf_offset = 0x14000,
961 	.cap_offset = 0x70,
962 	.port_conf_offset = 0x104000,
970 	.cap_offset = 0x70,
971 	.port_conf_offset = 0x1300,
972 	.port_irq_status_offset = 0x0,
973 	.port_irq_enable_offset = 0x4,