Lines Matching +full:xgene1 +full:- +full:msi
1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
73 return readl(port->csr_base + reg); in xgene_pcie_readl()
78 writel(val, port->csr_base + reg); in xgene_pcie_writel()
91 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
93 cfg = bus->sysdata; in pcie_bus_to_port()
94 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
105 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
106 return port->cfg_base + AXI_EP_CFG_ACCESS; in xgene_pcie_get_cfg_base()
108 return port->cfg_base; in xgene_pcie_get_cfg_base()
121 b = bus->number; in xgene_pcie_set_rtdid_reg()
134 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
174 * we read the Vendor and Device ID of a non-existent device, the in xgene_pcie_config_read32()
181 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && in xgene_pcie_config_read32()
186 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in xgene_pcie_config_read32()
195 struct device *dev = &adev->dev; in xgene_get_csr_resource()
214 return -EINVAL; in xgene_get_csr_resource()
218 *res = *entry->res; in xgene_get_csr_resource()
225 struct device *dev = cfg->parent; in xgene_pcie_ecam_init()
233 return -ENOMEM; in xgene_pcie_ecam_init()
240 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr); in xgene_pcie_ecam_init()
241 if (IS_ERR(port->csr_base)) in xgene_pcie_ecam_init()
242 return PTR_ERR(port->csr_base); in xgene_pcie_ecam_init()
244 port->cfg_base = cfg->win; in xgene_pcie_ecam_init()
245 port->version = ipversion; in xgene_pcie_ecam_init()
247 cfg->priv = port; in xgene_pcie_ecam_init()
283 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; in xgene_pcie_set_ib_mask()
311 port->link_up = false; in xgene_pcie_linkup()
314 port->link_up = true; in xgene_pcie_linkup()
323 struct device *dev = port->dev; in xgene_pcie_init_port()
326 port->clk = clk_get(dev, NULL); in xgene_pcie_init_port()
327 if (IS_ERR(port->clk)) { in xgene_pcie_init_port()
329 return -ENODEV; in xgene_pcie_init_port()
332 rc = clk_prepare_enable(port->clk); in xgene_pcie_init_port()
344 struct device *dev = port->dev; in xgene_pcie_map_reg()
348 port->csr_base = devm_pci_remap_cfg_resource(dev, res); in xgene_pcie_map_reg()
349 if (IS_ERR(port->csr_base)) in xgene_pcie_map_reg()
350 return PTR_ERR(port->csr_base); in xgene_pcie_map_reg()
353 port->cfg_base = devm_ioremap_resource(dev, res); in xgene_pcie_map_reg()
354 if (IS_ERR(port->cfg_base)) in xgene_pcie_map_reg()
355 return PTR_ERR(port->cfg_base); in xgene_pcie_map_reg()
356 port->cfg_addr = res->start; in xgene_pcie_map_reg()
365 struct device *dev = port->dev; in xgene_pcie_setup_ob_reg()
380 mask = ~(size - 1) | flag; in xgene_pcie_setup_ob_reg()
395 u64 addr = port->cfg_addr; in xgene_pcie_setup_cfg_reg()
406 struct device *dev = port->dev; in xgene_pcie_map_ranges()
408 resource_list_for_each_entry(window, &bridge->windows) { in xgene_pcie_map_ranges()
409 struct resource *res = window->res; in xgene_pcie_map_ranges()
417 pci_pio_to_address(res->start), in xgene_pcie_map_ranges()
418 res->start - window->offset); in xgene_pcie_map_ranges()
421 if (res->flags & IORESOURCE_PREFETCH) in xgene_pcie_map_ranges()
423 res->start, in xgene_pcie_map_ranges()
424 res->start - in xgene_pcie_map_ranges()
425 window->offset); in xgene_pcie_map_ranges()
428 res->start, in xgene_pcie_map_ranges()
429 res->start - in xgene_pcie_map_ranges()
430 window->offset); in xgene_pcie_map_ranges()
436 return -EINVAL; in xgene_pcie_map_ranges()
454 * X-Gene PCIe support maximum 3 inbound memory regions
474 return -EINVAL; in xgene_pcie_select_ib_reg()
480 void __iomem *cfg_base = port->cfg_base; in xgene_pcie_setup_ib_reg()
481 struct device *dev = port->dev; in xgene_pcie_setup_ib_reg()
484 u64 cpu_addr = range->cpu_addr; in xgene_pcie_setup_ib_reg()
485 u64 pci_addr = range->pci_addr; in xgene_pcie_setup_ib_reg()
486 u64 size = range->size; in xgene_pcie_setup_ib_reg()
487 u64 mask = ~(size - 1) | EN_REG; in xgene_pcie_setup_ib_reg()
492 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size); in xgene_pcie_setup_ib_reg()
494 dev_warn(dev, "invalid pcie dma-range config\n"); in xgene_pcie_setup_ib_reg()
498 if (range->flags & IORESOURCE_PREFETCH) in xgene_pcie_setup_ib_reg()
524 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1)); in xgene_pcie_setup_ib_reg()
529 struct device_node *np = port->node; in xgene_pcie_parse_map_dma_ranges()
532 struct device *dev = port->dev; in xgene_pcie_parse_map_dma_ranges()
536 dev_err(dev, "missing dma-ranges property\n"); in xgene_pcie_parse_map_dma_ranges()
537 return -EINVAL; in xgene_pcie_parse_map_dma_ranges()
540 /* Get the dma-ranges from DT */ in xgene_pcie_parse_map_dma_ranges()
542 u64 end = range.cpu_addr + range.size - 1; in xgene_pcie_parse_map_dma_ranges()
544 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n", in xgene_pcie_parse_map_dma_ranges()
562 struct device *dev = port->dev; in xgene_pcie_setup()
581 if (!port->link_up) in xgene_pcie_setup()
584 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1); in xgene_pcie_setup()
602 np = of_find_compatible_node(NULL, NULL, "apm,xgene1-msi"); in xgene_check_pcie_msi_ready()
614 struct device *dev = &pdev->dev; in xgene_pcie_probe()
615 struct device_node *dn = dev->of_node; in xgene_pcie_probe()
621 return dev_err_probe(&pdev->dev, -EPROBE_DEFER, in xgene_pcie_probe()
622 "MSI driver not ready\n"); in xgene_pcie_probe()
626 return -ENOMEM; in xgene_pcie_probe()
630 port->node = of_node_get(dn); in xgene_pcie_probe()
631 port->dev = dev; in xgene_pcie_probe()
632 port->version = XGENE_PCIE_IP_VER_1; in xgene_pcie_probe()
646 bridge->sysdata = port; in xgene_pcie_probe()
647 bridge->ops = &xgene_pcie_ops; in xgene_pcie_probe()
653 {.compatible = "apm,xgene-pcie",},
659 .name = "xgene-pcie",