Lines Matching +full:num +full:- +full:intr +full:- +full:inputs
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
25 #include <linux/irqchip/irq-msi-lib.h>
257 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
379 writel(value, pcie->afi + offset); in afi_writel()
384 return readl(pcie->afi + offset); in afi_readl()
390 writel(value, pcie->pads + offset); in pads_writel()
395 return readl(pcie->pads + offset); in pads_readl()
430 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
433 if (bus->number == 0) { in tegra_pcie_map_bus()
437 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_map_bus()
438 if (port->index + 1 == slot) { in tegra_pcie_map_bus()
439 addr = port->base + (where & ~3); in tegra_pcie_map_bus()
447 offset = tegra_pcie_conf_offset(bus->number, devfn, where); in tegra_pcie_map_bus()
450 base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); in tegra_pcie_map_bus()
454 addr = pcie->cfg + (offset & (SZ_4K - 1)); in tegra_pcie_map_bus()
463 if (bus->number == 0) in tegra_pcie_config_read()
473 if (bus->number == 0) in tegra_pcie_config_write()
488 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_get_pex_ctrl()
491 switch (port->index) { in tegra_pcie_port_get_pex_ctrl()
501 ret = soc->afi_pex2_ctrl; in tegra_pcie_port_get_pex_ctrl()
514 if (port->reset_gpio) { in tegra_pcie_port_reset()
515 gpiod_set_value(port->reset_gpio, 1); in tegra_pcie_port_reset()
517 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
519 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
524 if (port->reset_gpio) { in tegra_pcie_port_reset()
525 gpiod_set_value(port->reset_gpio, 0); in tegra_pcie_port_reset()
527 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
529 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
535 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_enable_rp_features()
539 value = readl(port->base + RP_VEND_CTL1); in tegra_pcie_enable_rp_features()
541 writel(value, port->base + RP_VEND_CTL1); in tegra_pcie_enable_rp_features()
544 value = readl(port->base + RP_VEND_XP); in tegra_pcie_enable_rp_features()
547 writel(value, port->base + RP_VEND_XP); in tegra_pcie_enable_rp_features()
553 value = readl(port->base + RP_VEND_XP_BIST); in tegra_pcie_enable_rp_features()
555 writel(value, port->base + RP_VEND_XP_BIST); in tegra_pcie_enable_rp_features()
557 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_enable_rp_features()
561 if (soc->update_clamp_threshold) { in tegra_pcie_enable_rp_features()
568 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_enable_rp_features()
573 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_program_ectl_settings()
576 value = readl(port->base + RP_ECTL_2_R1); in tegra_pcie_program_ectl_settings()
578 value |= soc->ectl.regs.rp_ectl_2_r1; in tegra_pcie_program_ectl_settings()
579 writel(value, port->base + RP_ECTL_2_R1); in tegra_pcie_program_ectl_settings()
581 value = readl(port->base + RP_ECTL_4_R1); in tegra_pcie_program_ectl_settings()
583 value |= soc->ectl.regs.rp_ectl_4_r1 << in tegra_pcie_program_ectl_settings()
585 writel(value, port->base + RP_ECTL_4_R1); in tegra_pcie_program_ectl_settings()
587 value = readl(port->base + RP_ECTL_5_R1); in tegra_pcie_program_ectl_settings()
589 value |= soc->ectl.regs.rp_ectl_5_r1; in tegra_pcie_program_ectl_settings()
590 writel(value, port->base + RP_ECTL_5_R1); in tegra_pcie_program_ectl_settings()
592 value = readl(port->base + RP_ECTL_6_R1); in tegra_pcie_program_ectl_settings()
594 value |= soc->ectl.regs.rp_ectl_6_r1; in tegra_pcie_program_ectl_settings()
595 writel(value, port->base + RP_ECTL_6_R1); in tegra_pcie_program_ectl_settings()
597 value = readl(port->base + RP_ECTL_2_R2); in tegra_pcie_program_ectl_settings()
599 value |= soc->ectl.regs.rp_ectl_2_r2; in tegra_pcie_program_ectl_settings()
600 writel(value, port->base + RP_ECTL_2_R2); in tegra_pcie_program_ectl_settings()
602 value = readl(port->base + RP_ECTL_4_R2); in tegra_pcie_program_ectl_settings()
604 value |= soc->ectl.regs.rp_ectl_4_r2 << in tegra_pcie_program_ectl_settings()
606 writel(value, port->base + RP_ECTL_4_R2); in tegra_pcie_program_ectl_settings()
608 value = readl(port->base + RP_ECTL_5_R2); in tegra_pcie_program_ectl_settings()
610 value |= soc->ectl.regs.rp_ectl_5_r2; in tegra_pcie_program_ectl_settings()
611 writel(value, port->base + RP_ECTL_5_R2); in tegra_pcie_program_ectl_settings()
613 value = readl(port->base + RP_ECTL_6_R2); in tegra_pcie_program_ectl_settings()
615 value |= soc->ectl.regs.rp_ectl_6_r2; in tegra_pcie_program_ectl_settings()
616 writel(value, port->base + RP_ECTL_6_R2); in tegra_pcie_program_ectl_settings()
621 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_apply_sw_fixup()
626 * instability in deskew logic on lane-0. Increase the deskew in tegra_pcie_apply_sw_fixup()
629 if (soc->program_deskew_time) { in tegra_pcie_apply_sw_fixup()
630 value = readl(port->base + RP_VEND_CTL0); in tegra_pcie_apply_sw_fixup()
633 writel(value, port->base + RP_VEND_CTL0); in tegra_pcie_apply_sw_fixup()
636 if (soc->update_fc_timer) { in tegra_pcie_apply_sw_fixup()
637 value = readl(port->base + RP_VEND_XP); in tegra_pcie_apply_sw_fixup()
639 value |= soc->update_fc_threshold; in tegra_pcie_apply_sw_fixup()
640 writel(value, port->base + RP_VEND_XP); in tegra_pcie_apply_sw_fixup()
645 * root port advertises both Gen-1 and Gen-2 speeds in Tegra. in tegra_pcie_apply_sw_fixup()
647 * only Gen-1 and after link is up, retrain link to Gen-2 speed in tegra_pcie_apply_sw_fixup()
649 value = readl(port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_apply_sw_fixup()
652 writel(value, port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_apply_sw_fixup()
658 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_enable()
662 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_enable()
665 if (soc->has_pex_clkreq_en) in tegra_pcie_port_enable()
670 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_enable()
674 if (soc->force_pca_enable) { in tegra_pcie_port_enable()
675 value = readl(port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
677 writel(value, port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
682 if (soc->ectl.enable) in tegra_pcie_port_enable()
691 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_disable()
695 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
697 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
700 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
702 if (soc->has_pex_clkreq_en) in tegra_pcie_port_disable()
706 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
709 value = afi_readl(port->pcie, AFI_PCIE_CONFIG); in tegra_pcie_port_disable()
710 value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_port_disable()
711 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index); in tegra_pcie_port_disable()
712 afi_writel(port->pcie, value, AFI_PCIE_CONFIG); in tegra_pcie_port_disable()
717 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_port_free()
718 struct device *dev = pcie->dev; in tegra_pcie_port_free()
720 devm_iounmap(dev, port->base); in tegra_pcie_port_free()
721 devm_release_mem_region(dev, port->regs.start, in tegra_pcie_port_free()
722 resource_size(&port->regs)); in tegra_pcie_port_free()
723 list_del(&port->list); in tegra_pcie_port_free()
730 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in tegra_pcie_fixup_class()
749 struct tegra_pcie *pcie = pdev->bus->sysdata; in tegra_pcie_map_irq()
756 irq = pcie->irq; in tegra_pcie_map_irq()
781 struct device *dev = pcie->dev; in tegra_pcie_isr()
819 * - 0xfdfc000000: I/O space
820 * - 0xfdfe000000: type 0 configuration space
821 * - 0xfdff000000: type 1 configuration space
822 * - 0xfe00000000: type 0 extended configuration space
823 * - 0xfe10000000: type 1 extended configuration space
832 size = resource_size(&pcie->cs); in tegra_pcie_setup_translations()
833 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START); in tegra_pcie_setup_translations()
836 resource_list_for_each_entry(entry, &bridge->windows) { in tegra_pcie_setup_translations()
838 struct resource *res = entry->res; in tegra_pcie_setup_translations()
846 axi_address = pci_pio_to_address(res->start); in tegra_pcie_setup_translations()
852 fpci_bar = (((res->start >> 12) & 0x0fffffff) << 4) | 0x1; in tegra_pcie_setup_translations()
853 axi_address = res->start; in tegra_pcie_setup_translations()
855 if (res->flags & IORESOURCE_PREFETCH) { in tegra_pcie_setup_translations()
880 if (pcie->soc->has_cache_bars) { in tegra_pcie_setup_translations()
897 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pll_wait()
903 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_pll_wait()
908 return -ETIMEDOUT; in tegra_pcie_pll_wait()
913 struct device *dev = pcie->dev; in tegra_pcie_phy_enable()
914 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_enable()
927 * Set up PHY PLL inputs select PLLE output as refclock, in tegra_pcie_phy_enable()
930 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
932 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; in tegra_pcie_phy_enable()
933 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
936 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
938 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
943 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
945 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
969 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_disable()
983 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
985 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
994 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_on()
998 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_on()
999 err = phy_power_on(port->phys[i]); in tegra_pcie_port_phy_power_on()
1011 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_off()
1015 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_off()
1016 err = phy_power_off(port->phys[i]); in tegra_pcie_port_phy_power_off()
1029 struct device *dev = pcie->dev; in tegra_pcie_phy_power_on()
1033 if (pcie->legacy_phy) { in tegra_pcie_phy_power_on()
1034 if (pcie->phy) in tegra_pcie_phy_power_on()
1035 err = phy_power_on(pcie->phy); in tegra_pcie_phy_power_on()
1045 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_on()
1050 port->index, err); in tegra_pcie_phy_power_on()
1060 struct device *dev = pcie->dev; in tegra_pcie_phy_power_off()
1064 if (pcie->legacy_phy) { in tegra_pcie_phy_power_off()
1065 if (pcie->phy) in tegra_pcie_phy_power_off()
1066 err = phy_power_off(pcie->phy); in tegra_pcie_phy_power_off()
1076 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_off()
1081 port->index, err); in tegra_pcie_phy_power_off()
1091 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_controller()
1096 if (pcie->phy) { in tegra_pcie_enable_controller()
1104 if (soc->has_pex_bias_ctrl) in tegra_pcie_enable_controller()
1110 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; in tegra_pcie_enable_controller()
1113 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_enable_controller()
1114 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_enable_controller()
1115 value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index); in tegra_pcie_enable_controller()
1120 if (soc->has_gen2) { in tegra_pcie_enable_controller()
1140 if (soc->has_intr_prsnt_sense) in tegra_pcie_enable_controller()
1155 struct device *dev = pcie->dev; in tegra_pcie_power_off()
1156 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_off()
1159 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_off()
1161 clk_disable_unprepare(pcie->pll_e); in tegra_pcie_power_off()
1162 if (soc->has_cml_clk) in tegra_pcie_power_off()
1163 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_off()
1164 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_off()
1166 if (!dev->pm_domain) in tegra_pcie_power_off()
1169 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_off()
1176 struct device *dev = pcie->dev; in tegra_pcie_power_on()
1177 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_on()
1180 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_power_on()
1181 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_on()
1182 reset_control_assert(pcie->pex_rst); in tegra_pcie_power_on()
1184 if (!dev->pm_domain) in tegra_pcie_power_on()
1188 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1192 if (!dev->pm_domain) { in tegra_pcie_power_on()
1205 err = clk_prepare_enable(pcie->afi_clk); in tegra_pcie_power_on()
1211 if (soc->has_cml_clk) { in tegra_pcie_power_on()
1212 err = clk_prepare_enable(pcie->cml_clk); in tegra_pcie_power_on()
1219 err = clk_prepare_enable(pcie->pll_e); in tegra_pcie_power_on()
1225 reset_control_deassert(pcie->afi_rst); in tegra_pcie_power_on()
1230 if (soc->has_cml_clk) in tegra_pcie_power_on()
1231 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_on()
1233 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_on()
1235 if (!dev->pm_domain) in tegra_pcie_power_on()
1238 regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1245 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_apply_pad_settings()
1248 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); in tegra_pcie_apply_pad_settings()
1250 if (soc->num_ports > 2) in tegra_pcie_apply_pad_settings()
1251 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); in tegra_pcie_apply_pad_settings()
1256 struct device *dev = pcie->dev; in tegra_pcie_clocks_get()
1257 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_clocks_get()
1259 pcie->pex_clk = devm_clk_get(dev, "pex"); in tegra_pcie_clocks_get()
1260 if (IS_ERR(pcie->pex_clk)) in tegra_pcie_clocks_get()
1261 return PTR_ERR(pcie->pex_clk); in tegra_pcie_clocks_get()
1263 pcie->afi_clk = devm_clk_get(dev, "afi"); in tegra_pcie_clocks_get()
1264 if (IS_ERR(pcie->afi_clk)) in tegra_pcie_clocks_get()
1265 return PTR_ERR(pcie->afi_clk); in tegra_pcie_clocks_get()
1267 pcie->pll_e = devm_clk_get(dev, "pll_e"); in tegra_pcie_clocks_get()
1268 if (IS_ERR(pcie->pll_e)) in tegra_pcie_clocks_get()
1269 return PTR_ERR(pcie->pll_e); in tegra_pcie_clocks_get()
1271 if (soc->has_cml_clk) { in tegra_pcie_clocks_get()
1272 pcie->cml_clk = devm_clk_get(dev, "cml"); in tegra_pcie_clocks_get()
1273 if (IS_ERR(pcie->cml_clk)) in tegra_pcie_clocks_get()
1274 return PTR_ERR(pcie->cml_clk); in tegra_pcie_clocks_get()
1282 struct device *dev = pcie->dev; in tegra_pcie_resets_get()
1284 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex"); in tegra_pcie_resets_get()
1285 if (IS_ERR(pcie->pex_rst)) in tegra_pcie_resets_get()
1286 return PTR_ERR(pcie->pex_rst); in tegra_pcie_resets_get()
1288 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi"); in tegra_pcie_resets_get()
1289 if (IS_ERR(pcie->afi_rst)) in tegra_pcie_resets_get()
1290 return PTR_ERR(pcie->afi_rst); in tegra_pcie_resets_get()
1292 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x"); in tegra_pcie_resets_get()
1293 if (IS_ERR(pcie->pcie_xrst)) in tegra_pcie_resets_get()
1294 return PTR_ERR(pcie->pcie_xrst); in tegra_pcie_resets_get()
1301 struct device *dev = pcie->dev; in tegra_pcie_phys_get_legacy()
1304 pcie->phy = devm_phy_optional_get(dev, "pcie"); in tegra_pcie_phys_get_legacy()
1305 if (IS_ERR(pcie->phy)) { in tegra_pcie_phys_get_legacy()
1306 err = PTR_ERR(pcie->phy); in tegra_pcie_phys_get_legacy()
1311 err = phy_init(pcie->phy); in tegra_pcie_phys_get_legacy()
1317 pcie->legacy_phy = true; in tegra_pcie_phys_get_legacy()
1330 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index); in devm_of_phy_optional_get_index()
1332 return ERR_PTR(-ENOMEM); in devm_of_phy_optional_get_index()
1342 struct device *dev = port->pcie->dev; in tegra_pcie_port_get_phys()
1347 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL); in tegra_pcie_port_get_phys()
1348 if (!port->phys) in tegra_pcie_port_get_phys()
1349 return -ENOMEM; in tegra_pcie_port_get_phys()
1351 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_get_phys()
1352 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i); in tegra_pcie_port_get_phys()
1366 port->phys[i] = phy; in tegra_pcie_port_get_phys()
1374 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phys_get()
1375 struct device_node *np = pcie->dev->of_node; in tegra_pcie_phys_get()
1379 if (!soc->has_gen2 || of_property_present(np, "phys")) in tegra_pcie_phys_get()
1382 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_get()
1394 struct device *dev = pcie->dev; in tegra_pcie_phys_put()
1397 if (pcie->legacy_phy) { in tegra_pcie_phys_put()
1398 err = phy_exit(pcie->phy); in tegra_pcie_phys_put()
1404 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_put()
1405 for (i = 0; i < port->lanes; i++) { in tegra_pcie_phys_put()
1406 err = phy_exit(port->phys[i]); in tegra_pcie_phys_put()
1416 struct device *dev = pcie->dev; in tegra_pcie_get_resources()
1419 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_get_resources()
1434 if (soc->program_uphy) { in tegra_pcie_get_resources()
1442 pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads"); in tegra_pcie_get_resources()
1443 if (IS_ERR(pcie->pads)) { in tegra_pcie_get_resources()
1444 err = PTR_ERR(pcie->pads); in tegra_pcie_get_resources()
1448 pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi"); in tegra_pcie_get_resources()
1449 if (IS_ERR(pcie->afi)) { in tegra_pcie_get_resources()
1450 err = PTR_ERR(pcie->afi); in tegra_pcie_get_resources()
1457 err = -EADDRNOTAVAIL; in tegra_pcie_get_resources()
1461 pcie->cs = *res; in tegra_pcie_get_resources()
1464 resource_set_size(&pcie->cs, SZ_4K); in tegra_pcie_get_resources()
1466 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs); in tegra_pcie_get_resources()
1467 if (IS_ERR(pcie->cfg)) { in tegra_pcie_get_resources()
1468 err = PTR_ERR(pcie->cfg); in tegra_pcie_get_resources()
1473 err = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_get_resources()
1477 pcie->irq = err; in tegra_pcie_get_resources()
1479 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); in tegra_pcie_get_resources()
1488 if (soc->program_uphy) in tegra_pcie_get_resources()
1496 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_put_resources()
1498 if (pcie->irq > 0) in tegra_pcie_put_resources()
1499 free_irq(pcie->irq, pcie); in tegra_pcie_put_resources()
1501 if (soc->program_uphy) in tegra_pcie_put_resources()
1509 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_pme_turnoff()
1510 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pme_turnoff()
1516 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1519 ack_bit = soc->ports[port->index].pme.ack_bit; in tegra_pcie_pme_turnoff()
1520 err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val, in tegra_pcie_pme_turnoff()
1523 dev_err(pcie->dev, "PME Ack is not received on port: %d\n", in tegra_pcie_pme_turnoff()
1524 port->index); in tegra_pcie_pme_turnoff()
1529 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1537 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_irq()
1538 struct device *dev = pcie->dev; in tegra_pcie_msi_irq()
1551 ret = generic_handle_domain_irq(msi->domain, index); in tegra_pcie_msi_irq()
1573 unsigned int index = d->hwirq / 32; in tegra_msi_irq_ack()
1576 afi_writel(pcie, BIT(d->hwirq % 32), AFI_MSI_VEC(index)); in tegra_msi_irq_ack()
1583 unsigned int index = d->hwirq / 32; in tegra_msi_irq_mask()
1587 spin_lock_irqsave(&msi->mask_lock, flags); in tegra_msi_irq_mask()
1589 value &= ~BIT(d->hwirq % 32); in tegra_msi_irq_mask()
1591 spin_unlock_irqrestore(&msi->mask_lock, flags); in tegra_msi_irq_mask()
1598 unsigned int index = d->hwirq / 32; in tegra_msi_irq_unmask()
1602 spin_lock_irqsave(&msi->mask_lock, flags); in tegra_msi_irq_unmask()
1604 value |= BIT(d->hwirq % 32); in tegra_msi_irq_unmask()
1606 spin_unlock_irqrestore(&msi->mask_lock, flags); in tegra_msi_irq_unmask()
1613 msg->address_lo = lower_32_bits(msi->phys); in tegra_compose_msi_msg()
1614 msg->address_hi = upper_32_bits(msi->phys); in tegra_compose_msi_msg()
1615 msg->data = data->hwirq; in tegra_compose_msi_msg()
1629 struct tegra_msi *msi = domain->host_data; in tegra_msi_domain_alloc()
1633 mutex_lock(&msi->map_lock); in tegra_msi_domain_alloc()
1635 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); in tegra_msi_domain_alloc()
1637 mutex_unlock(&msi->map_lock); in tegra_msi_domain_alloc()
1640 return -ENOSPC; in tegra_msi_domain_alloc()
1644 &tegra_msi_bottom_chip, domain->host_data, in tegra_msi_domain_alloc()
1656 struct tegra_msi *msi = domain->host_data; in tegra_msi_domain_free()
1658 mutex_lock(&msi->map_lock); in tegra_msi_domain_free()
1660 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); in tegra_msi_domain_free()
1662 mutex_unlock(&msi->map_lock); in tegra_msi_domain_free()
1685 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); in tegra_allocate_domains()
1693 msi->domain = msi_create_parent_irq_domain(&info, &tegra_msi_parent_ops); in tegra_allocate_domains()
1694 if (!msi->domain) { in tegra_allocate_domains()
1695 dev_err(pcie->dev, "failed to create MSI domain\n"); in tegra_allocate_domains()
1696 return -ENOMEM; in tegra_allocate_domains()
1703 irq_domain_remove(msi->domain); in tegra_free_domains()
1708 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_msi_setup()
1709 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_setup()
1710 struct device *dev = pcie->dev; in tegra_pcie_msi_setup()
1713 mutex_init(&msi->map_lock); in tegra_pcie_msi_setup()
1714 spin_lock_init(&msi->mask_lock); in tegra_pcie_msi_setup()
1726 msi->irq = err; in tegra_pcie_msi_setup()
1728 irq_set_chained_handler_and_data(msi->irq, tegra_pcie_msi_irq, pcie); in tegra_pcie_msi_setup()
1730 /* Though the PCIe controller can address >32-bit address space, to in tegra_pcie_msi_setup()
1731 * facilitate endpoints that support only 32-bit MSI target address, in tegra_pcie_msi_setup()
1732 * the mask is set to 32-bit to make sure that MSI target address is in tegra_pcie_msi_setup()
1733 * always a 32-bit address in tegra_pcie_msi_setup()
1741 msi->virt = dma_alloc_attrs(dev, PAGE_SIZE, &msi->phys, GFP_KERNEL, in tegra_pcie_msi_setup()
1743 if (!msi->virt) { in tegra_pcie_msi_setup()
1745 err = -ENOMEM; in tegra_pcie_msi_setup()
1752 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in tegra_pcie_msi_setup()
1762 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_msi()
1763 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_enable_msi()
1767 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); in tegra_pcie_enable_msi()
1768 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); in tegra_pcie_enable_msi()
1773 bitmap_to_arr32(msi_state, msi->used, INT_PCI_MSI_NR); in tegra_pcie_enable_msi()
1785 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_teardown()
1788 dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys, in tegra_pcie_msi_teardown()
1792 irq = irq_find_mapping(msi->domain, i); in tegra_pcie_msi_teardown()
1797 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in tegra_pcie_msi_teardown()
1827 struct device *dev = pcie->dev; in tegra_pcie_get_xbar_config()
1828 struct device_node *np = dev->of_node; in tegra_pcie_get_xbar_config()
1830 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_xbar_config()
1854 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") || in tegra_pcie_get_xbar_config()
1855 of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_xbar_config()
1867 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_xbar_config()
1884 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_xbar_config()
1887 dev_info(dev, "single-mode configuration\n"); in tegra_pcie_get_xbar_config()
1892 dev_info(dev, "dual-mode configuration\n"); in tegra_pcie_get_xbar_config()
1898 return -EINVAL; in tegra_pcie_get_xbar_config()
1914 snprintf(property, 32, "%s-supply", supplies[i].supply); in of_regulator_bulk_available()
1925 * supplies that didn't match the hardware inputs. This happened to work for a
1926 * number of cases but is not future proof. However to preserve backwards-
1932 struct device *dev = pcie->dev; in tegra_pcie_get_legacy_regulators()
1933 struct device_node *np = dev->of_node; in tegra_pcie_get_legacy_regulators()
1935 if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) in tegra_pcie_get_legacy_regulators()
1936 pcie->num_supplies = 3; in tegra_pcie_get_legacy_regulators()
1937 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) in tegra_pcie_get_legacy_regulators()
1938 pcie->num_supplies = 2; in tegra_pcie_get_legacy_regulators()
1940 if (pcie->num_supplies == 0) { in tegra_pcie_get_legacy_regulators()
1942 return -ENODEV; in tegra_pcie_get_legacy_regulators()
1945 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_legacy_regulators()
1946 sizeof(*pcie->supplies), in tegra_pcie_get_legacy_regulators()
1948 if (!pcie->supplies) in tegra_pcie_get_legacy_regulators()
1949 return -ENOMEM; in tegra_pcie_get_legacy_regulators()
1951 pcie->supplies[0].supply = "pex-clk"; in tegra_pcie_get_legacy_regulators()
1952 pcie->supplies[1].supply = "vdd"; in tegra_pcie_get_legacy_regulators()
1954 if (pcie->num_supplies > 2) in tegra_pcie_get_legacy_regulators()
1955 pcie->supplies[2].supply = "avdd"; in tegra_pcie_get_legacy_regulators()
1957 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies); in tegra_pcie_get_legacy_regulators()
1971 struct device *dev = pcie->dev; in tegra_pcie_get_regulators()
1972 struct device_node *np = dev->of_node; in tegra_pcie_get_regulators()
1975 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_regulators()
1976 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
1978 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1979 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1981 if (!pcie->supplies) in tegra_pcie_get_regulators()
1982 return -ENOMEM; in tegra_pcie_get_regulators()
1984 pcie->supplies[i++].supply = "dvdd-pex"; in tegra_pcie_get_regulators()
1985 pcie->supplies[i++].supply = "hvdd-pex-pll"; in tegra_pcie_get_regulators()
1986 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
1987 pcie->supplies[i++].supply = "vddio-pexctl-aud"; in tegra_pcie_get_regulators()
1988 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_regulators()
1989 pcie->num_supplies = 3; in tegra_pcie_get_regulators()
1991 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1992 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1994 if (!pcie->supplies) in tegra_pcie_get_regulators()
1995 return -ENOMEM; in tegra_pcie_get_regulators()
1997 pcie->supplies[i++].supply = "hvddio-pex"; in tegra_pcie_get_regulators()
1998 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
1999 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2000 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { in tegra_pcie_get_regulators()
2001 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
2003 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2004 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2006 if (!pcie->supplies) in tegra_pcie_get_regulators()
2007 return -ENOMEM; in tegra_pcie_get_regulators()
2009 pcie->supplies[i++].supply = "avddio-pex"; in tegra_pcie_get_regulators()
2010 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
2011 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
2012 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2013 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_regulators()
2024 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + in tegra_pcie_get_regulators()
2027 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2028 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2030 if (!pcie->supplies) in tegra_pcie_get_regulators()
2031 return -ENOMEM; in tegra_pcie_get_regulators()
2033 pcie->supplies[i++].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
2034 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
2035 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2036 pcie->supplies[i++].supply = "avdd-plle"; in tegra_pcie_get_regulators()
2039 pcie->supplies[i++].supply = "avdd-pexa"; in tegra_pcie_get_regulators()
2040 pcie->supplies[i++].supply = "vdd-pexa"; in tegra_pcie_get_regulators()
2044 pcie->supplies[i++].supply = "avdd-pexb"; in tegra_pcie_get_regulators()
2045 pcie->supplies[i++].supply = "vdd-pexb"; in tegra_pcie_get_regulators()
2047 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_regulators()
2048 pcie->num_supplies = 5; in tegra_pcie_get_regulators()
2050 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2051 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2053 if (!pcie->supplies) in tegra_pcie_get_regulators()
2054 return -ENOMEM; in tegra_pcie_get_regulators()
2056 pcie->supplies[0].supply = "avdd-pex"; in tegra_pcie_get_regulators()
2057 pcie->supplies[1].supply = "vdd-pex"; in tegra_pcie_get_regulators()
2058 pcie->supplies[2].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
2059 pcie->supplies[3].supply = "avdd-plle"; in tegra_pcie_get_regulators()
2060 pcie->supplies[4].supply = "vddio-pex-clk"; in tegra_pcie_get_regulators()
2063 if (of_regulator_bulk_available(dev->of_node, pcie->supplies, in tegra_pcie_get_regulators()
2064 pcie->num_supplies)) in tegra_pcie_get_regulators()
2065 return devm_regulator_bulk_get(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2066 pcie->supplies); in tegra_pcie_get_regulators()
2075 devm_kfree(dev, pcie->supplies); in tegra_pcie_get_regulators()
2076 pcie->num_supplies = 0; in tegra_pcie_get_regulators()
2083 struct device *dev = pcie->dev; in tegra_pcie_parse_dt()
2084 struct device_node *np = dev->of_node; in tegra_pcie_parse_dt()
2085 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_parse_dt()
2103 if (index < 1 || index > soc->num_ports) in tegra_pcie_parse_dt()
2104 return dev_err_probe(dev, -EINVAL, in tegra_pcie_parse_dt()
2107 index--; in tegra_pcie_parse_dt()
2109 err = of_property_read_u32(port, "nvidia,num-lanes", &value); in tegra_pcie_parse_dt()
2115 return dev_err_probe(dev, -EINVAL, in tegra_pcie_parse_dt()
2125 mask |= ((1 << value) - 1) << lane; in tegra_pcie_parse_dt()
2130 return -ENOMEM; in tegra_pcie_parse_dt()
2132 err = of_address_to_resource(port, 0, &rp->regs); in tegra_pcie_parse_dt()
2136 INIT_LIST_HEAD(&rp->list); in tegra_pcie_parse_dt()
2137 rp->index = index; in tegra_pcie_parse_dt()
2138 rp->lanes = value; in tegra_pcie_parse_dt()
2139 rp->pcie = pcie; in tegra_pcie_parse_dt()
2140 rp->np = port; in tegra_pcie_parse_dt()
2142 rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs); in tegra_pcie_parse_dt()
2143 if (IS_ERR(rp->base)) in tegra_pcie_parse_dt()
2144 return PTR_ERR(rp->base); in tegra_pcie_parse_dt()
2146 label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index); in tegra_pcie_parse_dt()
2148 return -ENOMEM; in tegra_pcie_parse_dt()
2151 * Returns -ENOENT if reset-gpios property is not populated in tegra_pcie_parse_dt()
2155 rp->reset_gpio = devm_fwnode_gpiod_get(dev, in tegra_pcie_parse_dt()
2160 if (IS_ERR(rp->reset_gpio)) { in tegra_pcie_parse_dt()
2161 if (PTR_ERR(rp->reset_gpio) == -ENOENT) in tegra_pcie_parse_dt()
2162 rp->reset_gpio = NULL; in tegra_pcie_parse_dt()
2164 return dev_err_probe(dev, PTR_ERR(rp->reset_gpio), in tegra_pcie_parse_dt()
2168 list_add_tail(&rp->list, &pcie->ports); in tegra_pcie_parse_dt()
2171 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); in tegra_pcie_parse_dt()
2191 struct device *dev = port->pcie->dev; in tegra_pcie_port_check_link()
2196 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2199 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2205 value = readl(port->base + RP_VEND_XP); in tegra_pcie_port_check_link()
2211 } while (--timeout); in tegra_pcie_port_check_link()
2214 dev_dbg(dev, "link %u down, retrying\n", port->index); in tegra_pcie_port_check_link()
2221 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_port_check_link()
2227 } while (--timeout); in tegra_pcie_port_check_link()
2231 } while (--retries); in tegra_pcie_port_check_link()
2238 struct device *dev = pcie->dev; in tegra_pcie_change_link_speed()
2243 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_change_link_speed()
2250 value = readl(port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_change_link_speed()
2253 writel(value, port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_change_link_speed()
2262 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2271 port->index); in tegra_pcie_change_link_speed()
2274 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2276 writel(value, port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2281 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2290 port->index); in tegra_pcie_change_link_speed()
2296 struct device *dev = pcie->dev; in tegra_pcie_enable_ports()
2299 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2301 port->index, port->lanes); in tegra_pcie_enable_ports()
2307 reset_control_deassert(pcie->pcie_xrst); in tegra_pcie_enable_ports()
2309 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2313 dev_info(dev, "link %u down, ignoring\n", port->index); in tegra_pcie_enable_ports()
2319 if (pcie->soc->has_gen2) in tegra_pcie_enable_ports()
2327 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_disable_ports()
2329 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_disable_ports()
2474 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2475 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2476 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2477 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2478 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2485 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_start()
2487 if (list_empty(&pcie->ports)) in tegra_pcie_ports_seq_start()
2492 return seq_list_start(&pcie->ports, *pos); in tegra_pcie_ports_seq_start()
2497 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_next()
2499 return seq_list_next(v, &pcie->ports, pos); in tegra_pcie_ports_seq_next()
2514 value = readl(port->base + RP_VEND_XP); in tegra_pcie_ports_seq_show()
2519 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_ports_seq_show()
2524 seq_printf(s, "%2u ", port->index); in tegra_pcie_ports_seq_show()
2551 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_debugfs_exit()
2552 pcie->debugfs = NULL; in tegra_pcie_debugfs_exit()
2557 pcie->debugfs = debugfs_create_dir("pcie", NULL); in tegra_pcie_debugfs_init()
2559 debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, pcie, in tegra_pcie_debugfs_init()
2565 struct device *dev = &pdev->dev; in tegra_pcie_probe()
2572 return -ENOMEM; in tegra_pcie_probe()
2575 host->sysdata = pcie; in tegra_pcie_probe()
2578 pcie->soc = of_device_get_match_data(dev); in tegra_pcie_probe()
2579 INIT_LIST_HEAD(&pcie->ports); in tegra_pcie_probe()
2580 pcie->dev = dev; in tegra_pcie_probe()
2598 pm_runtime_enable(pcie->dev); in tegra_pcie_probe()
2599 err = pm_runtime_get_sync(pcie->dev); in tegra_pcie_probe()
2605 host->ops = &tegra_pcie_ops; in tegra_pcie_probe()
2606 host->map_irq = tegra_pcie_map_irq; in tegra_pcie_probe()
2620 pm_runtime_put_sync(pcie->dev); in tegra_pcie_probe()
2621 pm_runtime_disable(pcie->dev); in tegra_pcie_probe()
2637 pci_stop_root_bus(host->bus); in tegra_pcie_remove()
2638 pci_remove_root_bus(host->bus); in tegra_pcie_remove()
2639 pm_runtime_put_sync(pcie->dev); in tegra_pcie_remove()
2640 pm_runtime_disable(pcie->dev); in tegra_pcie_remove()
2647 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_remove()
2657 list_for_each_entry(port, &pcie->ports, list) in tegra_pcie_pm_suspend()
2668 if (pcie->soc->program_uphy) { in tegra_pcie_pm_suspend()
2674 reset_control_assert(pcie->pex_rst); in tegra_pcie_pm_suspend()
2675 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_pm_suspend()
2709 err = clk_prepare_enable(pcie->pex_clk); in tegra_pcie_pm_resume()
2715 reset_control_deassert(pcie->pex_rst); in tegra_pcie_pm_resume()
2717 if (pcie->soc->program_uphy) { in tegra_pcie_pm_resume()
2731 reset_control_assert(pcie->pex_rst); in tegra_pcie_pm_resume()
2732 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_pm_resume()
2748 .name = "tegra-pcie",