Lines Matching +full:dt +full:- +full:binding +full:- +full:check
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
380 writel(value, pcie->afi + offset); in afi_writel()
385 return readl(pcie->afi + offset); in afi_readl()
391 writel(value, pcie->pads + offset); in pads_writel()
396 return readl(pcie->pads + offset); in pads_readl()
431 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
434 if (bus->number == 0) { in tegra_pcie_map_bus()
438 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_map_bus()
439 if (port->index + 1 == slot) { in tegra_pcie_map_bus()
440 addr = port->base + (where & ~3); in tegra_pcie_map_bus()
448 offset = tegra_pcie_conf_offset(bus->number, devfn, where); in tegra_pcie_map_bus()
451 base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); in tegra_pcie_map_bus()
455 addr = pcie->cfg + (offset & (SZ_4K - 1)); in tegra_pcie_map_bus()
464 if (bus->number == 0) in tegra_pcie_config_read()
474 if (bus->number == 0) in tegra_pcie_config_write()
489 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_get_pex_ctrl()
492 switch (port->index) { in tegra_pcie_port_get_pex_ctrl()
502 ret = soc->afi_pex2_ctrl; in tegra_pcie_port_get_pex_ctrl()
515 if (port->reset_gpio) { in tegra_pcie_port_reset()
516 gpiod_set_value(port->reset_gpio, 1); in tegra_pcie_port_reset()
518 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
520 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
525 if (port->reset_gpio) { in tegra_pcie_port_reset()
526 gpiod_set_value(port->reset_gpio, 0); in tegra_pcie_port_reset()
528 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_reset()
530 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_reset()
536 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_enable_rp_features()
540 value = readl(port->base + RP_VEND_CTL1); in tegra_pcie_enable_rp_features()
542 writel(value, port->base + RP_VEND_CTL1); in tegra_pcie_enable_rp_features()
545 value = readl(port->base + RP_VEND_XP); in tegra_pcie_enable_rp_features()
548 writel(value, port->base + RP_VEND_XP); in tegra_pcie_enable_rp_features()
554 value = readl(port->base + RP_VEND_XP_BIST); in tegra_pcie_enable_rp_features()
556 writel(value, port->base + RP_VEND_XP_BIST); in tegra_pcie_enable_rp_features()
558 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_enable_rp_features()
562 if (soc->update_clamp_threshold) { in tegra_pcie_enable_rp_features()
569 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_enable_rp_features()
574 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_program_ectl_settings()
577 value = readl(port->base + RP_ECTL_2_R1); in tegra_pcie_program_ectl_settings()
579 value |= soc->ectl.regs.rp_ectl_2_r1; in tegra_pcie_program_ectl_settings()
580 writel(value, port->base + RP_ECTL_2_R1); in tegra_pcie_program_ectl_settings()
582 value = readl(port->base + RP_ECTL_4_R1); in tegra_pcie_program_ectl_settings()
584 value |= soc->ectl.regs.rp_ectl_4_r1 << in tegra_pcie_program_ectl_settings()
586 writel(value, port->base + RP_ECTL_4_R1); in tegra_pcie_program_ectl_settings()
588 value = readl(port->base + RP_ECTL_5_R1); in tegra_pcie_program_ectl_settings()
590 value |= soc->ectl.regs.rp_ectl_5_r1; in tegra_pcie_program_ectl_settings()
591 writel(value, port->base + RP_ECTL_5_R1); in tegra_pcie_program_ectl_settings()
593 value = readl(port->base + RP_ECTL_6_R1); in tegra_pcie_program_ectl_settings()
595 value |= soc->ectl.regs.rp_ectl_6_r1; in tegra_pcie_program_ectl_settings()
596 writel(value, port->base + RP_ECTL_6_R1); in tegra_pcie_program_ectl_settings()
598 value = readl(port->base + RP_ECTL_2_R2); in tegra_pcie_program_ectl_settings()
600 value |= soc->ectl.regs.rp_ectl_2_r2; in tegra_pcie_program_ectl_settings()
601 writel(value, port->base + RP_ECTL_2_R2); in tegra_pcie_program_ectl_settings()
603 value = readl(port->base + RP_ECTL_4_R2); in tegra_pcie_program_ectl_settings()
605 value |= soc->ectl.regs.rp_ectl_4_r2 << in tegra_pcie_program_ectl_settings()
607 writel(value, port->base + RP_ECTL_4_R2); in tegra_pcie_program_ectl_settings()
609 value = readl(port->base + RP_ECTL_5_R2); in tegra_pcie_program_ectl_settings()
611 value |= soc->ectl.regs.rp_ectl_5_r2; in tegra_pcie_program_ectl_settings()
612 writel(value, port->base + RP_ECTL_5_R2); in tegra_pcie_program_ectl_settings()
614 value = readl(port->base + RP_ECTL_6_R2); in tegra_pcie_program_ectl_settings()
616 value |= soc->ectl.regs.rp_ectl_6_r2; in tegra_pcie_program_ectl_settings()
617 writel(value, port->base + RP_ECTL_6_R2); in tegra_pcie_program_ectl_settings()
622 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_apply_sw_fixup()
627 * instability in deskew logic on lane-0. Increase the deskew in tegra_pcie_apply_sw_fixup()
630 if (soc->program_deskew_time) { in tegra_pcie_apply_sw_fixup()
631 value = readl(port->base + RP_VEND_CTL0); in tegra_pcie_apply_sw_fixup()
634 writel(value, port->base + RP_VEND_CTL0); in tegra_pcie_apply_sw_fixup()
637 if (soc->update_fc_timer) { in tegra_pcie_apply_sw_fixup()
638 value = readl(port->base + RP_VEND_XP); in tegra_pcie_apply_sw_fixup()
640 value |= soc->update_fc_threshold; in tegra_pcie_apply_sw_fixup()
641 writel(value, port->base + RP_VEND_XP); in tegra_pcie_apply_sw_fixup()
646 * root port advertises both Gen-1 and Gen-2 speeds in Tegra. in tegra_pcie_apply_sw_fixup()
648 * only Gen-1 and after link is up, retrain link to Gen-2 speed in tegra_pcie_apply_sw_fixup()
650 value = readl(port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_apply_sw_fixup()
653 writel(value, port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_apply_sw_fixup()
659 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_enable()
663 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_enable()
666 if (soc->has_pex_clkreq_en) in tegra_pcie_port_enable()
671 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_enable()
675 if (soc->force_pca_enable) { in tegra_pcie_port_enable()
676 value = readl(port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
678 writel(value, port->base + RP_VEND_CTL2); in tegra_pcie_port_enable()
683 if (soc->ectl.enable) in tegra_pcie_port_enable()
692 const struct tegra_pcie_soc *soc = port->pcie->soc; in tegra_pcie_port_disable()
696 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
698 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
701 value = afi_readl(port->pcie, ctrl); in tegra_pcie_port_disable()
703 if (soc->has_pex_clkreq_en) in tegra_pcie_port_disable()
707 afi_writel(port->pcie, value, ctrl); in tegra_pcie_port_disable()
710 value = afi_readl(port->pcie, AFI_PCIE_CONFIG); in tegra_pcie_port_disable()
711 value |= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_port_disable()
712 value |= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index); in tegra_pcie_port_disable()
713 afi_writel(port->pcie, value, AFI_PCIE_CONFIG); in tegra_pcie_port_disable()
718 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_port_free()
719 struct device *dev = pcie->dev; in tegra_pcie_port_free()
721 devm_iounmap(dev, port->base); in tegra_pcie_port_free()
722 devm_release_mem_region(dev, port->regs.start, in tegra_pcie_port_free()
723 resource_size(&port->regs)); in tegra_pcie_port_free()
724 list_del(&port->list); in tegra_pcie_port_free()
731 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in tegra_pcie_fixup_class()
750 struct tegra_pcie *pcie = pdev->bus->sysdata; in tegra_pcie_map_irq()
757 irq = pcie->irq; in tegra_pcie_map_irq()
782 struct device *dev = pcie->dev; in tegra_pcie_isr()
820 * - 0xfdfc000000: I/O space
821 * - 0xfdfe000000: type 0 configuration space
822 * - 0xfdff000000: type 1 configuration space
823 * - 0xfe00000000: type 0 extended configuration space
824 * - 0xfe10000000: type 1 extended configuration space
833 size = resource_size(&pcie->cs); in tegra_pcie_setup_translations()
834 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START); in tegra_pcie_setup_translations()
837 resource_list_for_each_entry(entry, &bridge->windows) { in tegra_pcie_setup_translations()
839 struct resource *res = entry->res; in tegra_pcie_setup_translations()
847 axi_address = pci_pio_to_address(res->start); in tegra_pcie_setup_translations()
853 fpci_bar = (((res->start >> 12) & 0x0fffffff) << 4) | 0x1; in tegra_pcie_setup_translations()
854 axi_address = res->start; in tegra_pcie_setup_translations()
856 if (res->flags & IORESOURCE_PREFETCH) { in tegra_pcie_setup_translations()
881 if (pcie->soc->has_cache_bars) { in tegra_pcie_setup_translations()
898 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pll_wait()
904 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_pll_wait()
909 return -ETIMEDOUT; in tegra_pcie_pll_wait()
914 struct device *dev = pcie->dev; in tegra_pcie_phy_enable()
915 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_enable()
931 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
933 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; in tegra_pcie_phy_enable()
934 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
937 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
939 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
944 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
946 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
970 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_disable()
984 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
986 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_disable()
995 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_on()
999 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_on()
1000 err = phy_power_on(port->phys[i]); in tegra_pcie_port_phy_power_on()
1012 struct device *dev = port->pcie->dev; in tegra_pcie_port_phy_power_off()
1016 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_phy_power_off()
1017 err = phy_power_off(port->phys[i]); in tegra_pcie_port_phy_power_off()
1030 struct device *dev = pcie->dev; in tegra_pcie_phy_power_on()
1034 if (pcie->legacy_phy) { in tegra_pcie_phy_power_on()
1035 if (pcie->phy) in tegra_pcie_phy_power_on()
1036 err = phy_power_on(pcie->phy); in tegra_pcie_phy_power_on()
1046 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_on()
1051 port->index, err); in tegra_pcie_phy_power_on()
1061 struct device *dev = pcie->dev; in tegra_pcie_phy_power_off()
1065 if (pcie->legacy_phy) { in tegra_pcie_phy_power_off()
1066 if (pcie->phy) in tegra_pcie_phy_power_off()
1067 err = phy_power_off(pcie->phy); in tegra_pcie_phy_power_off()
1077 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phy_power_off()
1082 port->index, err); in tegra_pcie_phy_power_off()
1092 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_controller()
1097 if (pcie->phy) { in tegra_pcie_enable_controller()
1105 if (soc->has_pex_bias_ctrl) in tegra_pcie_enable_controller()
1111 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; in tegra_pcie_enable_controller()
1114 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_enable_controller()
1115 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); in tegra_pcie_enable_controller()
1116 value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index); in tegra_pcie_enable_controller()
1121 if (soc->has_gen2) { in tegra_pcie_enable_controller()
1141 if (soc->has_intr_prsnt_sense) in tegra_pcie_enable_controller()
1156 struct device *dev = pcie->dev; in tegra_pcie_power_off()
1157 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_off()
1160 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_off()
1162 clk_disable_unprepare(pcie->pll_e); in tegra_pcie_power_off()
1163 if (soc->has_cml_clk) in tegra_pcie_power_off()
1164 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_off()
1165 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_off()
1167 if (!dev->pm_domain) in tegra_pcie_power_off()
1170 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_off()
1177 struct device *dev = pcie->dev; in tegra_pcie_power_on()
1178 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_on()
1181 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_power_on()
1182 reset_control_assert(pcie->afi_rst); in tegra_pcie_power_on()
1183 reset_control_assert(pcie->pex_rst); in tegra_pcie_power_on()
1185 if (!dev->pm_domain) in tegra_pcie_power_on()
1189 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1193 if (!dev->pm_domain) { in tegra_pcie_power_on()
1206 err = clk_prepare_enable(pcie->afi_clk); in tegra_pcie_power_on()
1212 if (soc->has_cml_clk) { in tegra_pcie_power_on()
1213 err = clk_prepare_enable(pcie->cml_clk); in tegra_pcie_power_on()
1220 err = clk_prepare_enable(pcie->pll_e); in tegra_pcie_power_on()
1226 reset_control_deassert(pcie->afi_rst); in tegra_pcie_power_on()
1231 if (soc->has_cml_clk) in tegra_pcie_power_on()
1232 clk_disable_unprepare(pcie->cml_clk); in tegra_pcie_power_on()
1234 clk_disable_unprepare(pcie->afi_clk); in tegra_pcie_power_on()
1236 if (!dev->pm_domain) in tegra_pcie_power_on()
1239 regulator_bulk_disable(pcie->num_supplies, pcie->supplies); in tegra_pcie_power_on()
1246 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_apply_pad_settings()
1249 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0); in tegra_pcie_apply_pad_settings()
1251 if (soc->num_ports > 2) in tegra_pcie_apply_pad_settings()
1252 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1); in tegra_pcie_apply_pad_settings()
1257 struct device *dev = pcie->dev; in tegra_pcie_clocks_get()
1258 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_clocks_get()
1260 pcie->pex_clk = devm_clk_get(dev, "pex"); in tegra_pcie_clocks_get()
1261 if (IS_ERR(pcie->pex_clk)) in tegra_pcie_clocks_get()
1262 return PTR_ERR(pcie->pex_clk); in tegra_pcie_clocks_get()
1264 pcie->afi_clk = devm_clk_get(dev, "afi"); in tegra_pcie_clocks_get()
1265 if (IS_ERR(pcie->afi_clk)) in tegra_pcie_clocks_get()
1266 return PTR_ERR(pcie->afi_clk); in tegra_pcie_clocks_get()
1268 pcie->pll_e = devm_clk_get(dev, "pll_e"); in tegra_pcie_clocks_get()
1269 if (IS_ERR(pcie->pll_e)) in tegra_pcie_clocks_get()
1270 return PTR_ERR(pcie->pll_e); in tegra_pcie_clocks_get()
1272 if (soc->has_cml_clk) { in tegra_pcie_clocks_get()
1273 pcie->cml_clk = devm_clk_get(dev, "cml"); in tegra_pcie_clocks_get()
1274 if (IS_ERR(pcie->cml_clk)) in tegra_pcie_clocks_get()
1275 return PTR_ERR(pcie->cml_clk); in tegra_pcie_clocks_get()
1283 struct device *dev = pcie->dev; in tegra_pcie_resets_get()
1285 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex"); in tegra_pcie_resets_get()
1286 if (IS_ERR(pcie->pex_rst)) in tegra_pcie_resets_get()
1287 return PTR_ERR(pcie->pex_rst); in tegra_pcie_resets_get()
1289 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi"); in tegra_pcie_resets_get()
1290 if (IS_ERR(pcie->afi_rst)) in tegra_pcie_resets_get()
1291 return PTR_ERR(pcie->afi_rst); in tegra_pcie_resets_get()
1293 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x"); in tegra_pcie_resets_get()
1294 if (IS_ERR(pcie->pcie_xrst)) in tegra_pcie_resets_get()
1295 return PTR_ERR(pcie->pcie_xrst); in tegra_pcie_resets_get()
1302 struct device *dev = pcie->dev; in tegra_pcie_phys_get_legacy()
1305 pcie->phy = devm_phy_optional_get(dev, "pcie"); in tegra_pcie_phys_get_legacy()
1306 if (IS_ERR(pcie->phy)) { in tegra_pcie_phys_get_legacy()
1307 err = PTR_ERR(pcie->phy); in tegra_pcie_phys_get_legacy()
1312 err = phy_init(pcie->phy); in tegra_pcie_phys_get_legacy()
1318 pcie->legacy_phy = true; in tegra_pcie_phys_get_legacy()
1331 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index); in devm_of_phy_optional_get_index()
1333 return ERR_PTR(-ENOMEM); in devm_of_phy_optional_get_index()
1343 struct device *dev = port->pcie->dev; in tegra_pcie_port_get_phys()
1348 port->phys = devm_kcalloc(dev, port->lanes, sizeof(phy), GFP_KERNEL); in tegra_pcie_port_get_phys()
1349 if (!port->phys) in tegra_pcie_port_get_phys()
1350 return -ENOMEM; in tegra_pcie_port_get_phys()
1352 for (i = 0; i < port->lanes; i++) { in tegra_pcie_port_get_phys()
1353 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i); in tegra_pcie_port_get_phys()
1367 port->phys[i] = phy; in tegra_pcie_port_get_phys()
1375 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phys_get()
1376 struct device_node *np = pcie->dev->of_node; in tegra_pcie_phys_get()
1380 if (!soc->has_gen2 || of_property_present(np, "phys")) in tegra_pcie_phys_get()
1383 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_get()
1395 struct device *dev = pcie->dev; in tegra_pcie_phys_put()
1398 if (pcie->legacy_phy) { in tegra_pcie_phys_put()
1399 err = phy_exit(pcie->phy); in tegra_pcie_phys_put()
1405 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_phys_put()
1406 for (i = 0; i < port->lanes; i++) { in tegra_pcie_phys_put()
1407 err = phy_exit(port->phys[i]); in tegra_pcie_phys_put()
1417 struct device *dev = pcie->dev; in tegra_pcie_get_resources()
1420 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_get_resources()
1435 if (soc->program_uphy) { in tegra_pcie_get_resources()
1443 pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads"); in tegra_pcie_get_resources()
1444 if (IS_ERR(pcie->pads)) { in tegra_pcie_get_resources()
1445 err = PTR_ERR(pcie->pads); in tegra_pcie_get_resources()
1449 pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi"); in tegra_pcie_get_resources()
1450 if (IS_ERR(pcie->afi)) { in tegra_pcie_get_resources()
1451 err = PTR_ERR(pcie->afi); in tegra_pcie_get_resources()
1458 err = -EADDRNOTAVAIL; in tegra_pcie_get_resources()
1462 pcie->cs = *res; in tegra_pcie_get_resources()
1465 resource_set_size(&pcie->cs, SZ_4K); in tegra_pcie_get_resources()
1467 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs); in tegra_pcie_get_resources()
1468 if (IS_ERR(pcie->cfg)) { in tegra_pcie_get_resources()
1469 err = PTR_ERR(pcie->cfg); in tegra_pcie_get_resources()
1478 pcie->irq = err; in tegra_pcie_get_resources()
1480 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie); in tegra_pcie_get_resources()
1489 if (soc->program_uphy) in tegra_pcie_get_resources()
1497 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_put_resources()
1499 if (pcie->irq > 0) in tegra_pcie_put_resources()
1500 free_irq(pcie->irq, pcie); in tegra_pcie_put_resources()
1502 if (soc->program_uphy) in tegra_pcie_put_resources()
1510 struct tegra_pcie *pcie = port->pcie; in tegra_pcie_pme_turnoff()
1511 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pme_turnoff()
1517 val |= (0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1520 ack_bit = soc->ports[port->index].pme.ack_bit; in tegra_pcie_pme_turnoff()
1521 err = readl_poll_timeout(pcie->afi + AFI_PCIE_PME, val, in tegra_pcie_pme_turnoff()
1524 dev_err(pcie->dev, "PME Ack is not received on port: %d\n", in tegra_pcie_pme_turnoff()
1525 port->index); in tegra_pcie_pme_turnoff()
1530 val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit); in tegra_pcie_pme_turnoff()
1538 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_irq()
1539 struct device *dev = pcie->dev; in tegra_pcie_msi_irq()
1552 ret = generic_handle_domain_irq(msi->domain, index); in tegra_pcie_msi_irq()
1574 unsigned int index = d->hwirq / 32; in tegra_msi_irq_ack()
1577 afi_writel(pcie, BIT(d->hwirq % 32), AFI_MSI_VEC(index)); in tegra_msi_irq_ack()
1584 unsigned int index = d->hwirq / 32; in tegra_msi_irq_mask()
1587 scoped_guard(raw_spinlock_irqsave, &msi->mask_lock) { in tegra_msi_irq_mask()
1589 value &= ~BIT(d->hwirq % 32); in tegra_msi_irq_mask()
1598 unsigned int index = d->hwirq / 32; in tegra_msi_irq_unmask()
1601 scoped_guard(raw_spinlock_irqsave, &msi->mask_lock) { in tegra_msi_irq_unmask()
1603 value |= BIT(d->hwirq % 32); in tegra_msi_irq_unmask()
1612 msg->address_lo = lower_32_bits(msi->phys); in tegra_compose_msi_msg()
1613 msg->address_hi = upper_32_bits(msi->phys); in tegra_compose_msi_msg()
1614 msg->data = data->hwirq; in tegra_compose_msi_msg()
1628 struct tegra_msi *msi = domain->host_data; in tegra_msi_domain_alloc()
1632 mutex_lock(&msi->map_lock); in tegra_msi_domain_alloc()
1634 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); in tegra_msi_domain_alloc()
1636 mutex_unlock(&msi->map_lock); in tegra_msi_domain_alloc()
1639 return -ENOSPC; in tegra_msi_domain_alloc()
1643 &tegra_msi_bottom_chip, domain->host_data, in tegra_msi_domain_alloc()
1655 struct tegra_msi *msi = domain->host_data; in tegra_msi_domain_free()
1657 mutex_lock(&msi->map_lock); in tegra_msi_domain_free()
1659 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); in tegra_msi_domain_free()
1661 mutex_unlock(&msi->map_lock); in tegra_msi_domain_free()
1684 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); in tegra_allocate_domains()
1692 msi->domain = msi_create_parent_irq_domain(&info, &tegra_msi_parent_ops); in tegra_allocate_domains()
1693 if (!msi->domain) { in tegra_allocate_domains()
1694 dev_err(pcie->dev, "failed to create MSI domain\n"); in tegra_allocate_domains()
1695 return -ENOMEM; in tegra_allocate_domains()
1702 irq_domain_remove(msi->domain); in tegra_free_domains()
1707 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_msi_setup()
1708 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_setup()
1709 struct device *dev = pcie->dev; in tegra_pcie_msi_setup()
1712 mutex_init(&msi->map_lock); in tegra_pcie_msi_setup()
1713 raw_spin_lock_init(&msi->mask_lock); in tegra_pcie_msi_setup()
1725 msi->irq = err; in tegra_pcie_msi_setup()
1727 irq_set_chained_handler_and_data(msi->irq, tegra_pcie_msi_irq, pcie); in tegra_pcie_msi_setup()
1729 /* Though the PCIe controller can address >32-bit address space, to in tegra_pcie_msi_setup()
1730 * facilitate endpoints that support only 32-bit MSI target address, in tegra_pcie_msi_setup()
1731 * the mask is set to 32-bit to make sure that MSI target address is in tegra_pcie_msi_setup()
1732 * always a 32-bit address in tegra_pcie_msi_setup()
1740 msi->virt = dma_alloc_attrs(dev, PAGE_SIZE, &msi->phys, GFP_KERNEL, in tegra_pcie_msi_setup()
1742 if (!msi->virt) { in tegra_pcie_msi_setup()
1744 err = -ENOMEM; in tegra_pcie_msi_setup()
1751 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in tegra_pcie_msi_setup()
1761 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_enable_msi()
1762 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_enable_msi()
1766 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST); in tegra_pcie_enable_msi()
1767 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST); in tegra_pcie_enable_msi()
1772 bitmap_to_arr32(msi_state, msi->used, INT_PCI_MSI_NR); in tegra_pcie_enable_msi()
1784 struct tegra_msi *msi = &pcie->msi; in tegra_pcie_msi_teardown()
1787 dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys, in tegra_pcie_msi_teardown()
1791 irq = irq_find_mapping(msi->domain, i); in tegra_pcie_msi_teardown()
1796 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in tegra_pcie_msi_teardown()
1826 struct device *dev = pcie->dev; in tegra_pcie_get_xbar_config()
1827 struct device_node *np = dev->of_node; in tegra_pcie_get_xbar_config()
1829 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_xbar_config()
1847 dev_info(dev, "wrong configuration updated in DT, " in tegra_pcie_get_xbar_config()
1853 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") || in tegra_pcie_get_xbar_config()
1854 of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_xbar_config()
1866 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_xbar_config()
1883 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_xbar_config()
1886 dev_info(dev, "single-mode configuration\n"); in tegra_pcie_get_xbar_config()
1891 dev_info(dev, "dual-mode configuration\n"); in tegra_pcie_get_xbar_config()
1897 return -EINVAL; in tegra_pcie_get_xbar_config()
1901 * Check whether a given set of supplies is available in a device tree node.
1902 * This is used to check whether the new or the legacy device tree bindings
1913 snprintf(property, 32, "%s-supply", supplies[i].supply); in of_regulator_bulk_available()
1923 * Old versions of the device tree binding for this device used a set of power
1925 * number of cases but is not future proof. However to preserve backwards-
1931 struct device *dev = pcie->dev; in tegra_pcie_get_legacy_regulators()
1932 struct device_node *np = dev->of_node; in tegra_pcie_get_legacy_regulators()
1934 if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) in tegra_pcie_get_legacy_regulators()
1935 pcie->num_supplies = 3; in tegra_pcie_get_legacy_regulators()
1936 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) in tegra_pcie_get_legacy_regulators()
1937 pcie->num_supplies = 2; in tegra_pcie_get_legacy_regulators()
1939 if (pcie->num_supplies == 0) { in tegra_pcie_get_legacy_regulators()
1941 return -ENODEV; in tegra_pcie_get_legacy_regulators()
1944 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_legacy_regulators()
1945 sizeof(*pcie->supplies), in tegra_pcie_get_legacy_regulators()
1947 if (!pcie->supplies) in tegra_pcie_get_legacy_regulators()
1948 return -ENOMEM; in tegra_pcie_get_legacy_regulators()
1950 pcie->supplies[0].supply = "pex-clk"; in tegra_pcie_get_legacy_regulators()
1951 pcie->supplies[1].supply = "vdd"; in tegra_pcie_get_legacy_regulators()
1953 if (pcie->num_supplies > 2) in tegra_pcie_get_legacy_regulators()
1954 pcie->supplies[2].supply = "avdd"; in tegra_pcie_get_legacy_regulators()
1956 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies); in tegra_pcie_get_legacy_regulators()
1970 struct device *dev = pcie->dev; in tegra_pcie_get_regulators()
1971 struct device_node *np = dev->of_node; in tegra_pcie_get_regulators()
1974 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) { in tegra_pcie_get_regulators()
1975 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
1977 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1978 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1980 if (!pcie->supplies) in tegra_pcie_get_regulators()
1981 return -ENOMEM; in tegra_pcie_get_regulators()
1983 pcie->supplies[i++].supply = "dvdd-pex"; in tegra_pcie_get_regulators()
1984 pcie->supplies[i++].supply = "hvdd-pex-pll"; in tegra_pcie_get_regulators()
1985 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
1986 pcie->supplies[i++].supply = "vddio-pexctl-aud"; in tegra_pcie_get_regulators()
1987 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) { in tegra_pcie_get_regulators()
1988 pcie->num_supplies = 3; in tegra_pcie_get_regulators()
1990 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, in tegra_pcie_get_regulators()
1991 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
1993 if (!pcie->supplies) in tegra_pcie_get_regulators()
1994 return -ENOMEM; in tegra_pcie_get_regulators()
1996 pcie->supplies[i++].supply = "hvddio-pex"; in tegra_pcie_get_regulators()
1997 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
1998 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
1999 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) { in tegra_pcie_get_regulators()
2000 pcie->num_supplies = 4; in tegra_pcie_get_regulators()
2002 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2003 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2005 if (!pcie->supplies) in tegra_pcie_get_regulators()
2006 return -ENOMEM; in tegra_pcie_get_regulators()
2008 pcie->supplies[i++].supply = "avddio-pex"; in tegra_pcie_get_regulators()
2009 pcie->supplies[i++].supply = "dvddio-pex"; in tegra_pcie_get_regulators()
2010 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
2011 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2012 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { in tegra_pcie_get_regulators()
2023 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) + in tegra_pcie_get_regulators()
2026 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2027 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2029 if (!pcie->supplies) in tegra_pcie_get_regulators()
2030 return -ENOMEM; in tegra_pcie_get_regulators()
2032 pcie->supplies[i++].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
2033 pcie->supplies[i++].supply = "hvdd-pex"; in tegra_pcie_get_regulators()
2034 pcie->supplies[i++].supply = "vddio-pex-ctl"; in tegra_pcie_get_regulators()
2035 pcie->supplies[i++].supply = "avdd-plle"; in tegra_pcie_get_regulators()
2038 pcie->supplies[i++].supply = "avdd-pexa"; in tegra_pcie_get_regulators()
2039 pcie->supplies[i++].supply = "vdd-pexa"; in tegra_pcie_get_regulators()
2043 pcie->supplies[i++].supply = "avdd-pexb"; in tegra_pcie_get_regulators()
2044 pcie->supplies[i++].supply = "vdd-pexb"; in tegra_pcie_get_regulators()
2046 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) { in tegra_pcie_get_regulators()
2047 pcie->num_supplies = 5; in tegra_pcie_get_regulators()
2049 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2050 sizeof(*pcie->supplies), in tegra_pcie_get_regulators()
2052 if (!pcie->supplies) in tegra_pcie_get_regulators()
2053 return -ENOMEM; in tegra_pcie_get_regulators()
2055 pcie->supplies[0].supply = "avdd-pex"; in tegra_pcie_get_regulators()
2056 pcie->supplies[1].supply = "vdd-pex"; in tegra_pcie_get_regulators()
2057 pcie->supplies[2].supply = "avdd-pex-pll"; in tegra_pcie_get_regulators()
2058 pcie->supplies[3].supply = "avdd-plle"; in tegra_pcie_get_regulators()
2059 pcie->supplies[4].supply = "vddio-pex-clk"; in tegra_pcie_get_regulators()
2062 if (of_regulator_bulk_available(dev->of_node, pcie->supplies, in tegra_pcie_get_regulators()
2063 pcie->num_supplies)) in tegra_pcie_get_regulators()
2064 return devm_regulator_bulk_get(dev, pcie->num_supplies, in tegra_pcie_get_regulators()
2065 pcie->supplies); in tegra_pcie_get_regulators()
2070 * tree binding. in tegra_pcie_get_regulators()
2072 dev_info(dev, "using legacy DT binding for power supplies\n"); in tegra_pcie_get_regulators()
2074 devm_kfree(dev, pcie->supplies); in tegra_pcie_get_regulators()
2075 pcie->num_supplies = 0; in tegra_pcie_get_regulators()
2082 struct device *dev = pcie->dev; in tegra_pcie_parse_dt()
2083 struct device_node *np = dev->of_node; in tegra_pcie_parse_dt()
2084 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_parse_dt()
2102 if (index < 1 || index > soc->num_ports) in tegra_pcie_parse_dt()
2103 return dev_err_probe(dev, -EINVAL, in tegra_pcie_parse_dt()
2106 index--; in tegra_pcie_parse_dt()
2108 err = of_property_read_u32(port, "nvidia,num-lanes", &value); in tegra_pcie_parse_dt()
2114 return dev_err_probe(dev, -EINVAL, in tegra_pcie_parse_dt()
2124 mask |= ((1 << value) - 1) << lane; in tegra_pcie_parse_dt()
2129 return -ENOMEM; in tegra_pcie_parse_dt()
2131 err = of_address_to_resource(port, 0, &rp->regs); in tegra_pcie_parse_dt()
2135 INIT_LIST_HEAD(&rp->list); in tegra_pcie_parse_dt()
2136 rp->index = index; in tegra_pcie_parse_dt()
2137 rp->lanes = value; in tegra_pcie_parse_dt()
2138 rp->pcie = pcie; in tegra_pcie_parse_dt()
2139 rp->np = port; in tegra_pcie_parse_dt()
2141 rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs); in tegra_pcie_parse_dt()
2142 if (IS_ERR(rp->base)) in tegra_pcie_parse_dt()
2143 return PTR_ERR(rp->base); in tegra_pcie_parse_dt()
2145 label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index); in tegra_pcie_parse_dt()
2147 return -ENOMEM; in tegra_pcie_parse_dt()
2150 * Returns -ENOENT if reset-gpios property is not populated in tegra_pcie_parse_dt()
2154 rp->reset_gpio = devm_fwnode_gpiod_get(dev, in tegra_pcie_parse_dt()
2159 if (IS_ERR(rp->reset_gpio)) { in tegra_pcie_parse_dt()
2160 if (PTR_ERR(rp->reset_gpio) == -ENOENT) in tegra_pcie_parse_dt()
2161 rp->reset_gpio = NULL; in tegra_pcie_parse_dt()
2163 return dev_err_probe(dev, PTR_ERR(rp->reset_gpio), in tegra_pcie_parse_dt()
2167 list_add_tail(&rp->list, &pcie->ports); in tegra_pcie_parse_dt()
2170 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); in tegra_pcie_parse_dt()
2190 struct device *dev = port->pcie->dev; in tegra_pcie_port_check_link()
2195 value = readl(port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2198 writel(value, port->base + RP_PRIV_MISC); in tegra_pcie_port_check_link()
2204 value = readl(port->base + RP_VEND_XP); in tegra_pcie_port_check_link()
2210 } while (--timeout); in tegra_pcie_port_check_link()
2213 dev_dbg(dev, "link %u down, retrying\n", port->index); in tegra_pcie_port_check_link()
2220 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_port_check_link()
2226 } while (--timeout); in tegra_pcie_port_check_link()
2230 } while (--retries); in tegra_pcie_port_check_link()
2237 struct device *dev = pcie->dev; in tegra_pcie_change_link_speed()
2242 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_change_link_speed()
2249 value = readl(port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_change_link_speed()
2252 writel(value, port->base + RP_LINK_CONTROL_STATUS_2); in tegra_pcie_change_link_speed()
2261 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2270 port->index); in tegra_pcie_change_link_speed()
2273 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2275 writel(value, port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2280 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_change_link_speed()
2289 port->index); in tegra_pcie_change_link_speed()
2295 struct device *dev = pcie->dev; in tegra_pcie_enable_ports()
2298 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2300 port->index, port->lanes); in tegra_pcie_enable_ports()
2306 reset_control_deassert(pcie->pcie_xrst); in tegra_pcie_enable_ports()
2308 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in tegra_pcie_enable_ports()
2312 dev_info(dev, "link %u down, ignoring\n", port->index); in tegra_pcie_enable_ports()
2318 if (pcie->soc->has_gen2) in tegra_pcie_enable_ports()
2326 reset_control_assert(pcie->pcie_xrst); in tegra_pcie_disable_ports()
2328 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_disable_ports()
2473 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2474 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2475 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2476 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2477 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2484 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_start()
2486 if (list_empty(&pcie->ports)) in tegra_pcie_ports_seq_start()
2491 return seq_list_start(&pcie->ports, *pos); in tegra_pcie_ports_seq_start()
2496 struct tegra_pcie *pcie = s->private; in tegra_pcie_ports_seq_next()
2498 return seq_list_next(v, &pcie->ports, pos); in tegra_pcie_ports_seq_next()
2513 value = readl(port->base + RP_VEND_XP); in tegra_pcie_ports_seq_show()
2518 value = readl(port->base + RP_LINK_CONTROL_STATUS); in tegra_pcie_ports_seq_show()
2523 seq_printf(s, "%2u ", port->index); in tegra_pcie_ports_seq_show()
2550 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_debugfs_exit()
2551 pcie->debugfs = NULL; in tegra_pcie_debugfs_exit()
2556 pcie->debugfs = debugfs_create_dir("pcie", NULL); in tegra_pcie_debugfs_init()
2558 debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs, pcie, in tegra_pcie_debugfs_init()
2564 struct device *dev = &pdev->dev; in tegra_pcie_probe()
2571 return -ENOMEM; in tegra_pcie_probe()
2574 host->sysdata = pcie; in tegra_pcie_probe()
2577 pcie->soc = of_device_get_match_data(dev); in tegra_pcie_probe()
2578 INIT_LIST_HEAD(&pcie->ports); in tegra_pcie_probe()
2579 pcie->dev = dev; in tegra_pcie_probe()
2597 pm_runtime_enable(pcie->dev); in tegra_pcie_probe()
2598 err = pm_runtime_get_sync(pcie->dev); in tegra_pcie_probe()
2604 host->ops = &tegra_pcie_ops; in tegra_pcie_probe()
2605 host->map_irq = tegra_pcie_map_irq; in tegra_pcie_probe()
2619 pm_runtime_put_sync(pcie->dev); in tegra_pcie_probe()
2620 pm_runtime_disable(pcie->dev); in tegra_pcie_probe()
2636 pci_stop_root_bus(host->bus); in tegra_pcie_remove()
2637 pci_remove_root_bus(host->bus); in tegra_pcie_remove()
2638 pm_runtime_put_sync(pcie->dev); in tegra_pcie_remove()
2639 pm_runtime_disable(pcie->dev); in tegra_pcie_remove()
2646 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in tegra_pcie_remove()
2656 list_for_each_entry(port, &pcie->ports, list) in tegra_pcie_pm_suspend()
2667 if (pcie->soc->program_uphy) { in tegra_pcie_pm_suspend()
2673 reset_control_assert(pcie->pex_rst); in tegra_pcie_pm_suspend()
2674 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_pm_suspend()
2708 err = clk_prepare_enable(pcie->pex_clk); in tegra_pcie_pm_resume()
2714 reset_control_deassert(pcie->pex_rst); in tegra_pcie_pm_resume()
2716 if (pcie->soc->program_uphy) { in tegra_pcie_pm_resume()
2730 reset_control_assert(pcie->pex_rst); in tegra_pcie_pm_resume()
2731 clk_disable_unprepare(pcie->pex_clk); in tegra_pcie_pm_resume()
2747 .name = "tegra-pcie",