Lines Matching +full:pcie +full:- +full:phy +full:- +full:3
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
19 #include <linux/phy/phy.h>
23 #include "pcie-designware.h"
30 #define PCL_PERST_NOE_REGVAL BIT(3)
49 #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
57 #define PCL_RCV_INTX_ALL_STATUS GENMASK(3, 0)
69 struct phy *phy; member
73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
104 val = readl(pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
109 writel(val, pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
111 uniphier_pcie_ltssm_enable(pcie, false); in uniphier_pcie_init_rc()
116 val = readl(pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
118 writel(val, pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
121 static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie) in uniphier_pcie_wait_rc() argument
127 ret = readl_poll_timeout(pcie->base + PCL_PIPEMON, status, in uniphier_pcie_wait_rc()
130 dev_err(pcie->pci.dev, in uniphier_pcie_wait_rc()
140 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_link_up() local
143 val = readl(pcie->base + PCL_STATUS_LINK); in uniphier_pcie_link_up()
151 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_start_link() local
153 uniphier_pcie_ltssm_enable(pcie, true); in uniphier_pcie_start_link()
160 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_stop_link() local
162 uniphier_pcie_ltssm_enable(pcie, false); in uniphier_pcie_stop_link()
165 static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie) in uniphier_pcie_irq_enable() argument
167 writel(PCL_RCV_INT_ALL_ENABLE, pcie->base + PCL_RCV_INT); in uniphier_pcie_irq_enable()
168 writel(PCL_RCV_INTX_ALL_ENABLE, pcie->base + PCL_RCV_INTX); in uniphier_pcie_irq_enable()
176 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_irq_mask() local
180 raw_spin_lock_irqsave(&pp->lock, flags); in uniphier_pcie_irq_mask()
182 val = readl(pcie->base + PCL_RCV_INTX); in uniphier_pcie_irq_mask()
184 writel(val, pcie->base + PCL_RCV_INTX); in uniphier_pcie_irq_mask()
186 raw_spin_unlock_irqrestore(&pp->lock, flags); in uniphier_pcie_irq_mask()
193 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_irq_unmask() local
197 raw_spin_lock_irqsave(&pp->lock, flags); in uniphier_pcie_irq_unmask()
199 val = readl(pcie->base + PCL_RCV_INTX); in uniphier_pcie_irq_unmask()
201 writel(val, pcie->base + PCL_RCV_INTX); in uniphier_pcie_irq_unmask()
203 raw_spin_unlock_irqrestore(&pp->lock, flags); in uniphier_pcie_irq_unmask()
217 irq_set_chip_data(irq, domain->host_data); in uniphier_pcie_intx_map()
230 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_irq_handler() local
236 val = readl(pcie->base + PCL_RCV_INT); in uniphier_pcie_irq_handler()
239 dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); in uniphier_pcie_irq_handler()
241 dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); in uniphier_pcie_irq_handler()
243 dev_dbg(pci->dev, "Root Error\n"); in uniphier_pcie_irq_handler()
245 dev_dbg(pci->dev, "PME Interrupt\n"); in uniphier_pcie_irq_handler()
247 writel(val, pcie->base + PCL_RCV_INT); in uniphier_pcie_irq_handler()
252 val = readl(pcie->base + PCL_RCV_INTX); in uniphier_pcie_irq_handler()
256 generic_handle_domain_irq(pcie->intx_irq_domain, bit); in uniphier_pcie_irq_handler()
264 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_config_intx_irq() local
265 struct device_node *np = pci->dev->of_node; in uniphier_pcie_config_intx_irq()
269 np_intc = of_get_child_by_name(np, "legacy-interrupt-controller"); in uniphier_pcie_config_intx_irq()
271 dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n"); in uniphier_pcie_config_intx_irq()
272 return -EINVAL; in uniphier_pcie_config_intx_irq()
275 pp->irq = irq_of_parse_and_map(np_intc, 0); in uniphier_pcie_config_intx_irq()
276 if (!pp->irq) { in uniphier_pcie_config_intx_irq()
277 dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n"); in uniphier_pcie_config_intx_irq()
278 ret = -EINVAL; in uniphier_pcie_config_intx_irq()
282 pcie->intx_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX, in uniphier_pcie_config_intx_irq()
284 if (!pcie->intx_irq_domain) { in uniphier_pcie_config_intx_irq()
285 dev_err(pci->dev, "Failed to get INTx domain\n"); in uniphier_pcie_config_intx_irq()
286 ret = -ENODEV; in uniphier_pcie_config_intx_irq()
290 irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler, in uniphier_pcie_config_intx_irq()
301 struct uniphier_pcie *pcie = to_uniphier_pcie(pci); in uniphier_pcie_host_init() local
308 uniphier_pcie_irq_enable(pcie); in uniphier_pcie_host_init()
317 static int uniphier_pcie_host_enable(struct uniphier_pcie *pcie) in uniphier_pcie_host_enable() argument
321 ret = clk_prepare_enable(pcie->clk); in uniphier_pcie_host_enable()
325 ret = reset_control_deassert(pcie->rst); in uniphier_pcie_host_enable()
329 uniphier_pcie_init_rc(pcie); in uniphier_pcie_host_enable()
331 ret = phy_init(pcie->phy); in uniphier_pcie_host_enable()
335 ret = uniphier_pcie_wait_rc(pcie); in uniphier_pcie_host_enable()
342 phy_exit(pcie->phy); in uniphier_pcie_host_enable()
344 reset_control_assert(pcie->rst); in uniphier_pcie_host_enable()
346 clk_disable_unprepare(pcie->clk); in uniphier_pcie_host_enable()
359 struct device *dev = &pdev->dev; in uniphier_pcie_probe()
360 struct uniphier_pcie *pcie; in uniphier_pcie_probe() local
363 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in uniphier_pcie_probe()
364 if (!pcie) in uniphier_pcie_probe()
365 return -ENOMEM; in uniphier_pcie_probe()
367 pcie->pci.dev = dev; in uniphier_pcie_probe()
368 pcie->pci.ops = &dw_pcie_ops; in uniphier_pcie_probe()
370 pcie->base = devm_platform_ioremap_resource_byname(pdev, "link"); in uniphier_pcie_probe()
371 if (IS_ERR(pcie->base)) in uniphier_pcie_probe()
372 return PTR_ERR(pcie->base); in uniphier_pcie_probe()
374 pcie->clk = devm_clk_get(dev, NULL); in uniphier_pcie_probe()
375 if (IS_ERR(pcie->clk)) in uniphier_pcie_probe()
376 return PTR_ERR(pcie->clk); in uniphier_pcie_probe()
378 pcie->rst = devm_reset_control_get_shared(dev, NULL); in uniphier_pcie_probe()
379 if (IS_ERR(pcie->rst)) in uniphier_pcie_probe()
380 return PTR_ERR(pcie->rst); in uniphier_pcie_probe()
382 pcie->phy = devm_phy_optional_get(dev, "pcie-phy"); in uniphier_pcie_probe()
383 if (IS_ERR(pcie->phy)) in uniphier_pcie_probe()
384 return PTR_ERR(pcie->phy); in uniphier_pcie_probe()
386 platform_set_drvdata(pdev, pcie); in uniphier_pcie_probe()
388 ret = uniphier_pcie_host_enable(pcie); in uniphier_pcie_probe()
392 pcie->pci.pp.ops = &uniphier_pcie_host_ops; in uniphier_pcie_probe()
394 return dw_pcie_host_init(&pcie->pci.pp); in uniphier_pcie_probe()
398 { .compatible = "socionext,uniphier-pcie", },
405 .name = "uniphier-pcie",